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Part IV. Communications Processor Module
address recognition on the frame. The receiver can receive physical (individual), group
(multicast), and broadcast addresses. Ethernet receive frame data is not written to memory
until the internal address recognition process completes, which improves bus usage with
frames not addressed to this station.
If a match is found, the Ethernet controller fetches the next RxBD and, if it is empty, starts
transferring the incoming frame to the RxBD associated data buffer. If a collision is
detected during the frame, the RxBDs associated with this frame are reused. Thus, there
will be no collision frames presented to you except late collisions, which indicate serious
LAN problems. When the data buffer has been Þlled, the Ethernet controller clears the E
bit in the RxBD and generates an interrupt if the I bit is set. If the incoming frame exceeds
the length of the data buffer, the Ethernet controller fetches the next RxBD in the table and,
if it is empty, continues transferring the rest of the frame to this buffer. The RxBD length is
determined by MRBLR in the SCC general-purpose parameter RAM, which should be at
least 64 bytes.
During reception, the Ethernet controller checks for a frame that is either too short or too
long. When the frame ends, the receive CRC Þeld is checked and written to the buffer. The
data length written to the last BD in the Ethernet frame is the length of the entire frame and
it enables the software to correctly recognize the frame-too-long condition.
The Ethernet controller then sets the L bit in the RxBD, writes the other frame status bits
into the RxBD, and clears the E bit. Then it generates a maskable interrupt, which indicates
that a frame has been received and is in memory. The Ethernet controller then waits for a
new frame. It receives serial data least-signiÞcant bit Þrst.
24.6 The Content-Addressable Memory (CAM)
Interface
The Ethernet controller has one option for connecting to an external CAMÑa serial
interface. The reject signal (REJECT) is used to signify that the current frame should be
discarded. The MPC8260Õs internal address recognition logic can be used in combination
with an external CAM. See Section 24.10, ÒSCC Ethernet Address Recognition.Ó
The MPC8260 outputs a receive start (RSTRT) signal when the start frame delimiter is
recognized. This signal is asserted for one bit time on the second destination address bit.
The CAM control logic uses RSTRT (in combination with the RXD and RCLK signals) to
store the destination or source address and generate writes to the CAM for address
recognition. In addition, the RENA signal supplied from the SIA can be used to abort the
comparison if a collision occurs on the receive frame.
After the comparison, the CAM control logic asserts the receive reject signal (REJECT), if
the current receive frame is rejected. The MPC8260Õs Ethernet controller then immediately
stops writing data to system memory and reuses the buffer(s) for the next frame. If the CAM
accepts the frame, the CAM control logic does nothing (REJECT is not asserted). However,
if REJECT is asserted, it must be done prior to the end of the receive frame.
MOTOROLA
Chapter 24. SCC Ethernet Mode
24-7
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