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Part III. The Hardware Interface
Clock
Address
PSDVAL
CSx
CSy
R/W
OE
Data
Figure 10-53. GPCM Read Followed by Read (ORx[29Ð30] = 10)
10.5.2 External Access Termination
External access termination is supported by the GPCM using GTA, which is synchronized
and sampled internally by the MPC8260. If, during a GPCM data phase (second cycle or
later), the sampled signal is asserted, it is converted to PSDVAL, which terminates the
current GPCM access. GTA should be asserted for one cycle. Note that because GTA is
synchronized, bus termination may occur up to two cycles after GTA assertion, so in case
of read cycle, the device still must output data as long is OE is asserted. The user selects
whether PSDVAL is generated internally or externally (by means of GTA assertion) by
resetting/setting BRx[SETA].
Figure 10-54 shows how a GPCM access is terminated by GTA assertion. Asserting GTA
terminates an access even if BRx[SETA] = 0 (internal PSDVAL generation).
10-60
Hold Time
MPC8260 PowerQUICC II UserÕs Manual
MOTOROLA
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