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Table 22-12. SCC BISYNC TxBD Status and Control Field Descriptions (Continued)
Bits
Name
8
TD
Transmit DLE.
0 No automatic DLE transmission can occur before the data buffer.
1 The transmitter sends a DLE character before sending the buffer, which saves writing the Þrst DLE to
a separate buffer in transparent mode. See TR for information on control characters.
9
TR
Transparent mode.
0 The transmitter enters and stays in normal mode after sending the buffer. The transmitter
automatically inserts SYNCs if an underrun condition occurs.
1 The transmitter enters or stays in transparent mode after sending the buffer. It automatically inserts
DLEÐSYNC pairs if an underrun occurs (the controller Þnishes a buffer with L = 0 and the next BD is
not available). It also checks all characters before sending them. If a DLE is detected, another DLE is
sent automatically. Insert a DLE or program the controller to insert one before each control
character. The transmitter calculates the CRC16 BCS even if PSMR[BCS] is programmed to LRC.
Initialize PTCRC to CRC16 before setting TR.
10
B
BCS enable.
0 The buffer consists of characters that are excluded from BCS accumulation.
1 The buffer consists of characters that are included in BCS accumulation.
11Ð13 Ñ
Reserved, should be cleared.
14
UN
Underrun. Set when the BISYNC controller encounters a transmitter underrun error while sending the
associated data buffer. The CPM writes UN after it sends the associated buffer.
15
CT
CTS lost. The CP sets CT when CTS is lost during message transmission after it sends the data buffer.
Data length and buffer pointer Þelds are described in Section 19.2, ÒSCC Buffer
Descriptors (BDs).Ó Although it is never modiÞed by the CP, data length should be greater
than zero. The CPM writes these Þelds after it Þnishes sending the buffer.
22.14 BISYNC Event Register (SCCE)/BISYNC Mask
Register (SCCM)
The BISYNC controller uses the SCC event register (SCCE) to report events recognized by
the BISYNC channel and to generate interrupts. When an event is recognized, the controller
sets the corresponding SCCE bit. Interrupts are enabled by setting, and masked by clearing,
the equivalent bits in the BISYNC mask register (SCCM). SCCE bits are reset by writing
ones; writing zeros has no effect. Unmasked bits must be reset before the CP negates the
internal interrupt request signal.
Bit
0
1
Field
Ñ
Reset
R/W
Addr
0x11A10 (SCCE1); 0x11A30 (SCCE2); 0x11A50 (SCCE3); 0x11A70 (SCCE4)
0x11A14 (SCCM1); 0x11A34 (SCCM2); 0x11A54 (SCCM3); 0x11A74 (SCCM4)
Figure 22-8. BISYNC Event Register (SCCE)/BISYNC Mask Register (SCCM)
MOTOROLA
2
3
4
5
6
GLR GLT DCC
0000_0000_0000_0000
Chapter 22. SCC BISYNC Mode
Part IV. Communications Processor Module
Description
7
8
9
10
Ñ
GRA
Ñ
R/W
11
12
13
14
TXE RCH BSY TXB RXB
22-15
15
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