Local Bus Arbitration Level Registers (Lcl_Alrh And Lcl_Acrl) - Motorola MPC8260 PowerQUICC II User Manual

Part II. ConÞguration and Reset
Table 4-11 describes LCL_ACR register bits.
Bits Name
0Ð1 Ñ Reserved, should be cleared.
2 DBGD Data bus grant delay. SpeciÞes the minimum number of data tenure wait states for PowerPC
master-initiated data operations. This is the minimum delay between TS and DBG.
0 DBG is asserted with TS if the data bus is free.
1 DBG is asserted one cycle after TS if the data bus is not busy.
See Section 8.5.1, ÒData Bus Arbitration.Ó
3 Ñ Reserved, should be cleared.
4Ð7 PRKM Parking master. DeÞnes the parked master.
0000 CPM high request level
0001 CPM middle request level
0010 CPM low request level (default)
0011 Host bridge
Values 0100Ð1111 are reserved.
4.3.2.5 Local Bus Arbitration Level Registers (LCL_ALRH and
LCL_ACRL)
The local bus arbitration level registers (LCL_ALRH and LCL_ALRL), shown in
Figure 4-26 and Figure 4-27, deÞnes arbitration priority for MPC8260 local bus masters 0Ð
7. Priority Þeld 0 has highest-priority. For information about the MPC8260 local bus master
indexes see LCL_ACR[PRKM] in Table 4-11.
Bit 0 1 2
Field Priority Field 0
Reset 0000
R/W
Addr
Bit 16 17 18
Field Priority Field 4
Reset 0100
R/W
Addr
LCL_ALRL, shown in Figure 4-27, deÞnes arbitration priority of MPC8260 local bus
masters 8Ð15.
4-30
Table 4-11. LCL_ACR Field Descriptions
3 4 5 6
Priority Field 1
0001
19 20 21 22
Priority Field 5
0101
Figure 4-26. LCL_ALRH
MPC8260 PowerQUICC II UserÕs Manual
Description
7 8 9 10
Priority Field 2
0010
R/W
0x10038
23 24 25 26
Priority Field 6
0110
R/W
0x10040
11 12 13 14
Priority Field 3
0011
27 28 29 30
Priority Field 7
0111
MOTOROLA
15
31