Motorola MPC8260 PowerQUICC II User Manual page 127

Internal
Abbreviation
Address
11029 Reserved
1102C IDMR2
1102D Reserved
11030 IDSR3
11031 Reserved
11034 IDMR3
11035 Reserved
11038 IDSR4
11039 Reserved
1103C IDMR4
1103DÐ112FF Reserved
11300 GFMR1
11304 FPSMR1
11308 FTODR1
1130A Reserved
1130C FDSR1
1130E Reserved
11310 FCCE1
11314 FCCM1
11318 FCCS1
11319 Reserved
1131C FTIRR1_PHY0 FCC1 transmit internal rate registers
1131D FTIRR1_PHY1
1131E FTIRR1_PHY2
1131F FTIRR1_PHY3
11320 GFMR2
11324 FPSMR2
MOTOROLA
Table 3-1. Internal Memory Map (Continued)
Name
Ñ
IDMA 2 mask register
Ñ
IDMA 3 event register
Ñ
IDMA 3 mask register
Ñ
IDMA 4 event register
Ñ
IDMA 4 mask register
Ñ
FCC1 general mode register
FCC1 protocol-speciÞc mode register
FCC1 transmit on demand register
Ñ
FCC1 data synchronization register
Ñ
FCC1 event register
FCC1 mask register
FCC1 status register
Ñ
for PHY0Ð3
FCC2 general mode register
FCC2 protocol-speciÞc mode register
Chapter 3. Memory Map
Size
24 bits
8 bits
24 bits
8 bits
24 bits
8 bits
24 bits
8 bits
24 bits
8 bits
707 bytes
FCC1
32 bits
32 bits
16 bits
2 bytes
16 bits
2 bytes
32 bits
32 bits
8 bits
3 bytes
8 bits
8 bits
8 bits
8 bits
FCC2
32 bits
32 bits
Part I. Overview
Section/Page Number
Ñ
18.8.4/18-22
Ñ
18.8.4/18-22
Ñ
18.8.4/18-22
Ñ
18.8.4/18-22
Ñ
18.8.4/18-22
Ñ
28.2/28-3
29.13.2/29-85 (ATM)
30.18.1/30-20 (Ethernet)
31.6/31-7 (HDLC)
28.5/28-7
Ñ
28.4/28-7
Ñ
29.13.3/29-87 (ATM)
30.18.2/30-21 (Ethernet)
31.9/31-14 (HDLC)
31.10/31-16 (HDLC)
Ñ
29.13.4/29-88 (ATM)
28.2/28-3
29.13.2/29-85 (ATM)
30.18.1/30-20 (Ethernet)
31.6/31-7 (HDLC)
3-7