Table of Contents
Advertisement
28.7.1 FCC Function Code Registers (FCRx)
The function code registers contain the transaction speciÞcation associated with SDMA
channel accesses to external memory. Figure 28-5 shows the format of the transmit and
receive function code registers, which reside at TSTATE[0Ð7] and RSTATE[0Ð7] in the
FCC parameter RAM (see Table 28-5).
Bits
0
Field
Ñ
FCRx Þelds are described in Table 28-6.
Bits Name
0Ð1
Ñ
Reserved, should be cleared.
2
GBL Global. Indicates whether the memory operation should be snooped.
0 Snooping disabled.
1 Snooping enabled.
3Ð4
BO
Byte ordering. Used to select the byte ordering of the buffer. If BO is modiÞed on-the-ßy, it takes effect
at the start of the next frame (Ethernet, HDLC, and transparent) or at the beginning of the next BD.
01 PowerPC little-endian byte ordering. As data is sent onto the serial line from the data buffer, the
LSB of the buffer double-word contains data to be sent earlier than the MSB of the same buffer
double-word.
10 Motorola byte ordering (normal operation). It is also called big-endian byte ordering. As data is sent
onto the serial line from the data buffer, the MSB of the buffer word contains data to be sent earlier
than the LSB of the same buffer word.
5
TC2
Transfer code. Contains the transfer code value of TC[2], used during this SDMA channel memory
access. TC[0Ð1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access.
6
DTB Indicates on what bus the data is located.
0 On the 60x bus.
1 On the local.
7
BDB Indicates on what bus the BDs are located.
0 On the 60x bus.
1 On the local bus.
28.8 Interrupts from the FCCs
Interrupt handling for each of the FCC channels is conÞgured on a global (per channel)
basis in the interrupt pending register (SIPNR_L) and interrupt mask register (SIMR_L).
One bit in each register is used to either mask, enable, or report an interrupt in an FCC
channel. The interrupt priority between the FCCs is programmable in the CPM interrupt
priority register (SCPRR_H). The interrupt vector register (SIVEC) indicates which
pending channel has highest priority. Registers within the FCCs manage interrupt handling
for FCC-speciÞc events.
MOTOROLA
Chapter 28. Fast Communications Controllers (FCCs)
1
2
GBL
Figure 28-5. Function Code Register (FCRx)
Table 28-6. FCRx Field Descriptions
Part IV. Communications Processor Module
3
4
BO
TC2
Description
5
6
DTB
BDB
28-13
7
Advertisement
Table of Contents
