Handling Scc Interrupts - Motorola MPC8260 PowerQUICC II User Manual

Part IV. Communications Processor Module
Table 19-6 describes RFCRx/TFCRx Þelds.
Bits Name
0Ð1 Ñ Reserved, should be cleared.
2 GBL Global
0 Snooping disabled.
1 Snooping enabled.
3Ð4 BO Byte ordering. Set BO to select the required byte ordering for the buffer. If BO is changed on-the-ßy,
it takes effect at the beginning of the next frame (Ethernet, HDLC, and transparent) or at the
beginning of the next BD.
00 Reserved
01 PowerPC little-endian.
1x Big-endian or true little-endian.
5 TC2 Transfer code. Contains the transfer code value of TC[2], used during this SDMA channel memory
access. TC[0Ð1] is driven with a 0b11 to identify this SDMA channel access as a DMA-type access.
6 DTB Data bus indicator
0 Use 60x bus for SDMA operation
1 Use local bus for SDMA operation
7 Ñ Reserved, should be cleared.

19.3.3 Handling SCC Interrupts

To allow interrupt handling for SCC-speciÞc events, event, mask, and status registers are
provided within each SCCÕs internal memory map area; see Table 19-7. Because interrupt
events are protocol-dependent, event descriptions are found in the speciÞc protocol
chapters.
Table 19-7. SCCx Event, Mask, and Status Registers
Register &
IMMR Offset
SCCEx SCC event register. This 16-bit register reports events recognized by any of the SCCs. When an event
0x11A10 (SCCE1); is recognized, the SCC sets its corresponding bit in SCCE, regardless of the corresponding mask bit.
0x11A30 (SCCE2); When the corresponding event occurs, an interrupt is signaled to the SIVEC register. Bits are cleared
0x11A50 (SCCE3); by writing ones (writing zeros has no effect). SCCE is cleared at reset and can be read at any time.
0x11A70 (SCCE4)
SCCMx SCC mask register. The 16-bit, read/write register allows interrupts to be enabled or disabled using
0x11A14 (SCCM1); the CPM for speciÞc events in each SCC channel. An interrupt is generated only if SCC interrupts in
0x11A34 (SCCM2); this channel are enabled in the SIU interrupt mask register (SIMR). If an SCCM bit is zero, the CPM
0x11A54 (SCCM3); does not proceed with interrupt handling when that event occurs. The SCCM and SCCE bit positions
0x11A74 (SCCM4) are identical.
SCCSx SCC status register. This 8-bit, read-only register allows monitoring of the real-time status of RXD.
0x11A17 (SCCS1);
0x11A37 (SCCS2);
0x11A57 (SCCS3);
0x11A77 (SCCS4)
19-16
Table 19-6. RFCRx /TFCRx Field Descriptions
MPC8260 PowerQUICC II UserÕs Manual
Description
Description
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