Scc, Fcc, And Mcc Relative Priority; Pit, Tmcnt, And Irq Relative Priority - Motorola MPC8260 PowerQUICC II User Manual

Part II. ConÞguration and Reset
Table 4-2. Interrupt Source Priority Levels (Continued)
Priority Level
66
67
68
69
70
71
72
73
Notice the lack of SDMA interrupt sources, which are reported through each individual
FCC, SCC, SMC, SPI, or I
channel bus error entry that is reported when a bus error occurs during an SDMA access.
There are two ways to add ßexibility to the table of CPM interrupt prioritiesÑthe FCC,
MCC, and SCC relative priority option, described in Section 4.2.2.1, ÒSCC, FCC, and
MCC Relative Priority,Ó and the highest priority option, described in Section 4.2.2.3,
ÒHighest Priority Interrupt.Ó

4.2.2.1 SCC, FCC, and MCC Relative Priority

The relative priority between the four SCCs, three FCCs, and MCC is programmable and
can be changed dynamically. In Table 4-2 there is no entry for SCC1ÐSCC4, MCC1Ð
MCC2, FCC1ÐFCC3, but rather there are entries for XCC1ÐXCC8 and YCC1ÐYCC8.
Each SCC can be mapped to any YCC location and each FCC and MCC can be mapped to
any XCC location. The SCC, FCC, and MCC priorities are programmed in the CPM
interrupt priority registers (SCPRR_H and SCPRR_L) and can be changed dynamically to
implement a rotating priority.
In addition, the grouping of the locations of the YCC entries has the following two options
¥ Group. In the group scheme, all SCCs are grouped together at the top of the priority
table, ahead of most other CPM interrupt sources. This scheme is ideal for
applications where all SCCs, FCCs, and MCCs function at a very high data rate and
interrupt latency is very important.
¥ Spread. In the spread scheme, priorities are spread over the table so other sources
can have lower interrupt latencies. This scheme is also programmed in the SICR but
cannot be changed dynamically.

4.2.2.2 PIT, TMCNT, and IRQ Relative Priority

The MPC8260 has seven general-purpose interrupt requests (IRQs), Þve of which, with the
PIT, and TMCNT, can be mapped to any XSIU location. IRQ6 and IRQ7 have Þxed
priority.
4-12
Interrupt Source Description
SMC1
YCC7 (spread)
SMC2
Parallel I/OÐPC1
Parallel I/OÐPC0
XSIU8 (GSIU = 1)
YCC8(spread)
Reserved
2
C channel. The only true SDMA interrupt source is the SDMA
MPC8260 PowerQUICC II UserÕs Manual
Multiple Events
Yes
Yes
Yes
No
No
No (TMCNT,PIT = Yes)
Yes
Ñ
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