Programming The Scc In Hdlc Mode; Scc Hdlc Commands - Motorola MPC8260 PowerQUICC II User Manual

Figure 21-2 shows 16- and 8-bit address recognition.
Flag Address
0x7E 0x68
HADDR1
HADDR2
HADDR3
HADDR4
Recognizes one 16-bit address (HADDR1) and
the 16-bit broadcast address (HADDR2)

21.5 Programming the SCC in HDLC Mode

HDLC mode is selected for an SCC by writing GSMR_L[MODE] = 0b0000. The HDLC
controller uses the same buffer and BD data structure as other modes and supports
multibuffer operation and address comparisons. Receive errors are reported through the
RxBD; transmit errors are reported through the TxBD.

21.6 SCC HDLC Commands

The transmit and receive commands are issued to the CP command register (CPCR).
Transmit commands are described in Table 21-2.
Command
After a hardware or software reset and a channel is enabled in the GSMR, the transmitter starts polling
STOP
the Þrst BD in the TxBD table every 64 Tx clocks, or immediately if TODR[TOD] = 1, and begins sending
TRANSMIT
data if TxBD[R] is set. If the SCC receives the
transmitter stops polling the BDs. If the SCC receives the command during transmission, transmission is
aborted after a maximum of 64 additional bits, the Tx FIFO is ßushed, and the current BD pointer TBPTR
is not advanced (no new BD is accessed). The transmitter then sends an abort sequence (0x7F) and
stops polling the BDs.
When not transmitting, the channel sends ßags or idles as programmed in the GSMR.
Note that if PSMR[MFF] = 1, multiple small frames could be ßushed from the Tx FIFO; a
command prevents this.
TRANSMIT
Stops transmission smoothly. Unlike a
GRACEFUL
frame is Þnished or immediately if no frame is being sent. SCCE[GRA] is set when transmission stops.
STOP
HDLC Tx parameters and Tx BDs can then be updated. TBPTR points to the next TxBD. Transmission
TRANSMIT
begins once TxBD[R] of the next BD is set and a
Enables frames to be sent on the transmit channel. The HDLC controller expects this command after a
RESTART
TRANSMIT STOP TRANSMIT
command, or after a transmitter error. The transmitter resumes from the current BD.
Resets the Tx parameters in the parameter RAM. Issue only when the transmitter is disabled.
INIT TX
PARAMETERS RX PARAMETERS
MOTOROLA
16-Bit Address Recognition
Address Control
0xAA 0x44
HMASK 0xFFFF
0xAA68
0xFFFF
0xAA68
0xAA68
Figure 21-2. HDLC Address Recognition
Table 21-2. Transmit Commands
STOP TRANSMIT
is issued and the channel in its GSMR is disabled, after a
resets both Tx and Rx parameters.
Chapter 21. SCC HDLC Mode
Part IV. Communications Processor Module
8-Bit Address Recognition
Flag
etc.
0x7E
HMASK
HADDR1
HADDR2
HADDR3
HADDR4
Recognizes a single 8-bit address (HADDR1)
Description
command while not transmitting, the
STOP TRANSMIT
command, it stops transmission after the current
command is issued.
RESTART TRANSMIT
Address Control
etc.
0x55 0x44
0x00FF
0xXX55
0xXX55
0xXX55
0xXX55
GRACEFUL STOP
GRACEFUL STOP TRANSMIT
INIT TX AND
21-5