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13.4 Command Set
The core issues commands to the CP by writing to the CP command register (CPCR). The
CPCR rarely needs to be accessed. For example, to terminate the transmission of an SCCÕs
frame without waiting until the end, a
command register (CPCR).
13.4.1 CP Command Register (CPCR)
The core should set CPCR[FLG], shown in Figure 13-6, when it issues a command and the
CP clears FLG after completing the command, thus indicating to the core that it is ready for
the next command. Subsequent commands to the CPCR can be given only after FLG is
clear. However, the software reset command issued by setting RST does not depend on the
state of FLG, but the core should still set FLG when setting RST.
Bits
0
1
Field
RST
Reset
R/W
Addr
Bits
16
17
Field
Ñ
Reset
R/W
Addr
Table 13-6 describes CPCR Þelds.
Table 13-6. CP Command Register Field Descriptions
Bit
Name
Description
0
RST
Software reset command. Set by the core and cleared by the CP. When this command is
executed, RST and FLG bit are cleared within two general system clocks. The CPM reset routine
is approximately 60 clocks long, but the user can begin initialization of the CPM immediately after
this command is issued.
RST is useful when the core wants to reset the registers and parameters for all the channels
(FCCs, SCCs, SMCs, SPI, I
command does not affect the serial interface (SIx) or parallel I/O registers.
1Ð5
PAGE
Indicates the parameter RAM page number associated with the sub-block being served. See the
SBC description for page numbers.
MOTOROLA
Chapter 13. Communications Processor Module Overview
STOP TX
2
3
4
5
PAGE
0000_0000_0000_0000
18
19
20
21
22
MCC channel number (MCN)
0000_0000_0000_0000
Figure 13-6. CP Command Register (CPCR)
2
C, MCC) as well as the CP and RISC timer tables. However, this
Part IV. Communications Processor Module
command must be issued through the CP
6
7
8
9
10
Sub-block code (SBC)
R/W
0x119CE
23
24
25
26
R/W
0x119D0
11
12
13
14
Ñ
27
28
29
30
Ñ
OPCODE
15
FLG
31
13-11
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