Motorola MPC8260 PowerQUICC II User Manual page 836

Part IV. Communications Processor Module
Table 29-24 describes AAL0 protocol-speciÞc TCT Þelds.
Table 29-24. AAL0-Specific TCT Field Descriptions
Offset Bits Name
0x10 0Ð7 Ñ
8 0
9 CR10
10 Ñ
11 ACHC
12Ð15 Ñ
0x12Ð Ñ Ñ
0x14
29.10.2.3.4 VBR Protocol-SpeciÞc TCTE
Figure 29-34 shows the VBR protocol-speciÞc TCTE.
0
Offset + 0x00
Offset + 0x02
Offset + 0x04
Offset + 0x06
Offset + 0x08
Offset + 0x0A
Offset + 0x0C VBR2
Offset + 0x0E-1E
Figure 29-34. Transmit Connection Table Extension (TCTE)ÑVBR Protocol-
Table 29-25 describes VBR protocol-speciÞc TCTE Þelds.
Table 29-25. VBR-Specific TCTE Field Descriptions
Offset Bits Name
0x00 Ñ SCR Sustain cell rate. Holds the sustain cell rate (in slots) permitted for this channel according to
the trafÞc contract. To pace the channelÕs sustain cell rate, the APC performs a continuous-
state leaky bucket algorithm (GCRA).
0x02 Ñ BT Burst tolerance. Holds the burst tolerance permitted for this channel according to the trafÞc
contract. The relationship between the BT and the maximum burst size (MBS) is BT=(MBS-2)
´ (SCR-PCR) + SCR.
0x04 Ñ OOBR Out-of-buffer rate. In out of buffer state (when the transmitter tries to open TxBD whose R bit
is not set) the APC reschedules the current channel according to OOBR rate.
29-56
Reserved, should be cleared.
Must be 0.
CRC-10
0 CRC10 insertion is disabled.
1 CRC10 insertion is enabled.
Reserved, should be cleared.
ATM cell header change
0 Normal operation ATM cell header is taken from AAL0 buffer.
1 VPI/VCI (28 bits) are taken from TCT.
Reserved, should be cleared.
Reserved, should be cleared.
1 2 3 4 5
Out of Buffer Rate (OOBR)
Sustain Rate Remainder (SRR)
Specific
MPC8260 PowerQUICC II UserÕs Manual
Description
6 7 8 9 10
SCR
Burst Tolerance (BT)
SCR Fraction (SCRF)
Sustain Rate (SR)
Ñ
Ñ
Description
11 12 13 14 15
MOTOROLA