Normal Operation - Motorola MPC8260 PowerQUICC II User Manual

Some parameter RAM values must be initialized before the FCC is enabled; other values
are initialized/written by the CP. Once initialized, most parameter RAM values do not need
to be accessed by user software because most activity centers around the TxBDs and
RxBDs rather than the parameter RAM. However, if the parameter RAM is accessed, note
the following:
¥ Parameter RAM can be read at any time.
¥ Tx parameter RAM can be written only when the transmitter is disabledÑafter a
STOP TRANSMIT
buffer/frame Þnishes transmitting after a
before a
RESTART TRANSMIT
¥ Rx parameter RAM can be written only when the receiver is disabled. Note the
command does not stop reception, but it does allow the user to extract
CLOSE RXBD
data from a partially full Rx buffer.
¥ See Section 28.12, ÒDisabling the FCCs On-the-Fly.Ó
Some parameters in Table 28-5 are not described and are listed only to provide information
for experienced users and for debugging. The user need not access these parameters in

normal operation.

Table 28-5. FCC Parameter RAM Common to All Protocols
1
Offset Name Width
0x00 RIPTR Hword Receive internal temporary data pointer. Used by microcode as a temporary buffer for
0x02 TIPTR Hword Transmit internal temporary data pointer. Used by microcode as a temporary buffer for
0x04 Ñ Hword Reserved, should be cleared.
0x06 MRBLR Hword Maximum receive buffer length (a multiple of 32 for all modes). The number of bytes that
0x08 RSTATE Word Receive internal state. The high byte, RSTATE[0Ð7], contains the function code register;
MOTOROLA Chapter 28. Fast Communications Controllers (FCCs)
command and before a
command.
data. Must be 32-byte aligned and the size of the internal buffer must be 32 bytes unless
it is stated otherwise in the protocol speciÞcation. For best performance, it should be
located in the following address ranges: 0x3000Ð0x4000 or 0xB000Ð0xC000.
data. Must be 32-byte aligned and the size of the internal buffer must be 32 bytes unless
it is stated otherwise in the protocol speciÞcation. For best performance it should be
located in the following address ranges: 0x3000Ð0x4000 or 0xB000Ð0xC000.
the FCC receiver writes to a receive buffer before moving to the next buffer. The receiver
can write fewer bytes to the buffer than MRBLR if a condition such as an error or end-of-
frame occurs, but it never exceeds the MRBLR value. Therefore, user-supplied buffers
should be at least as large as the MRBLR.
Note that FCC transmit buffers can have varying lengths by programming TxBD[Data
Length], as needed, and are not affected by the value in MRBLR.
MRBLR is not intended to be changed dynamically while an FCC is operating. Change
MRBLR only when the FCC receiver is disabled.
see Section 28.7.1, ÒFCC Function Code Registers (FCRx).Ó RSTATE[8Ð31] is used by
the CP and must be cleared initially.
Part IV. Communications Processor Module
command or after the
RESTART TRANSMIT
GRACEFUL STOP TRANSMIT
Description
command and
28-11