Address And Address Space Checking - Motorola MPC8260 PowerQUICC II User Manual

Part III. The Hardware Interface
selected according to the type of external access transacted. At every clock cycle, the
logical value of the external signals speciÞed in the RAM array is output on the
corresponding UPM pins.
Figure 10-4 shows a basic conÞguration.
Address (A),
Address
Type (AT)
Address
Comparator
Bank Select
MS/BS
Fields
Figure 10-4. Basic Memory Controller Operation
The SDRAM mode registers (LSDMR and PSDMR) deÞne the global parameters for the
60x and local SDRAM devices. Machine A/B/C mode registers (MxMR) deÞne most of the
global features for each UPM. GPCM parameters are deÞned in the option register (ORx).
Some SDRAM and UPM parameters are also deÞned in ORx.

10.2.1 Address and Address Space Checking

The deÞned base address is written to the BRx. The bank size is written to the ORx. Each
time a bus cycle access is requested on the 60x or local bus, addresses are compared with
each bank. If a match is found on a memory controller bank, the attributes deÞned in the
BRx and ORx for that bank are used to control the memory access. If a match is found in
more than one bank, the lowest-numbered bank handles the memory access (that is, bank 0
has priority over bank 1).
Note that although 60x bus accesses that hit a bank allocated to the local bus are transferred
to the local bus, local bus access hits to banks allocated to the 60x bus are ignored.
60x-to-local bus transactions has priority over regular memory bank hits.
10-8
Internal/External Memory Access Request Select
SDRAM Machine
MPC8260 PowerQUICC II UserÕs Manual
UPMx GPCM
Signals
Timing
Generator
MUX
External Signals
MOTOROLA