Motorola MPC8260 PowerQUICC II User Manual page 896

Part IV. Communications Processor Module
affect bit values. Unmasked FCCE bits must be cleared before the CP clears the internal
interrupt request.
Bits 0 1 2
Field
Reset
R/W
Addr
Ethernet Event Register (FCCE)/Mask Register (FCCM)
Figure 30-6.
Table 30-9 describes FCCE/FCCM Þelds.
Bits Name
0Ð7 Ñ Reserved, should be cleared.
8 GRA Graceful stop complete. A graceful stop, initiated by the
complete. When the command is issued, GRA is set as soon the transmitter Þnishes sending a frame
in progress. If no frame is in progress, GRA is set immediately.
9 RXC RX control. A control frame has been received (FSMR[FCE] must be set). As soon as the transmitter
Þnishes sending the current frame, a pause operation is performed.
10 TXC TX control. An out-of-sequence frame was sent.
11 TXE Tx error. An error occurred on the transmitter channel.
12 RXF Rx frame. Set when a complete frame is received on the Ethernet channel.
13 BSY Busy condition. Set when a frame is received and discarded due to a lack of buffers.
14 TXB Tx buffer. Set when a buffer has been sent on the Ethernet channel.
15 RXB Rx buffer. A buffer that was not a complete frame is received on the Ethernet channel.
Figure 30-7 shows interrupts that can be generated in the Ethernet protocol.
30-22
3 4 5 6
Ñ
0000_0000_0000_0000
0x11310 (FCCE1), 0x11330 (FCCE2), 0x11350 (FCCE3)/
0x11314 (FCCM1), 0x11334 (FCCM2), 0x11354 (FCCM3)
Table 30-9. FCCE/FCCM Field Descriptions
MPC8260 PowerQUICC II UserÕs Manual
7 8 9 10 11
GRA RXC TXC TXE RXF BSY TXB RXB
R/W
Description
GRACEFUL STOP TRANSMIT
12 13 14 15
command, is
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