Interrupt Configuration - Motorola MPC8260 PowerQUICC II User Manual

Part II. ConÞguration and Reset
¥ Two priority schemes for the SCCs: grouped, spread
¥ Programmable highest priority request
¥ Unique vector number for each interrupt source
4.2.1 Interrupt ConÞguration
Figure 4-8 shows the MPC8260 interrupt structure. The interrupt controller receives
interrupts from internal sources, such as the PIT or TMCNT, from the CPM, and from
external pins (port C parallel I/O pins).
IRQ[0Ð7]
Port C[0Ð15]
16
4-8
Software Watchdog Timer
Fall/
Level
16
TMCNT
Edge/
Fall
Timer1
Timer2
Timer3
Timer4
FCC1
FCC2
FCC3
MCC1
MCC2
SCC1
SCC2
SCC3
SCC4
SMC1
SMC2
SPI
IDMA1
IDMA2
IDMA3
IDMA4
SDMA
RISC Timers
Figure 4-8. MPC8260 Interrupt Structure
MPC8260 PowerQUICC II UserÕs Manual
OR
IRQ0
PIT
2
I C
MCP
PowerPC
Core
INT
MOTOROLA