Transfer Code Signals Tc[0Ð2]; Tbst And Tsiz[0Ð3] Signals And Size Of Transfer - Motorola MPC8260 PowerQUICC II User Manual

8.4.3.2 Transfer Code Signals TC[0Ð2]
The transfer code signals, TC[0Ð2], provide supplemental information about the
corresponding address (mainly regarding the source of the transaction). Note that TCx
signals can be used with the TT[0Ð4] and TBST to further deÞne the current transaction.
TC[0Ð2]
000
001
010
011
100
101
110
111
8.4.3.3 TBST and TSIZ[0Ð3] Signals and Size of Transfer
As shown in Table 8-4, the transfer size signals (TSIZ[0Ð3]) and the transfer burst signal
(TBST) together indicate the size of the requested data transfer. These signals can be used
with address bits A[27Ð31] and the device port size to determine which portion of the data
bus contains valid data for a write transaction or which portion of the bus should contain
valid data for a read transaction.
The MPC8260 uses four double-word burst transactions for transferring cache blocks. For
these transactions, TSIZ[0Ð3] are encoded as 0b0010, and address bits A[27Ð28] determine
which double-word is sent Þrst.
The MPC8260 supports critical-word-Þrst burst transactions (double-word-aligned) from
the processor. The MPC8260 transfers the critical double word of data Þrst, followed by the
double words from increasing addresses, wrapping back to the beginning of the eight-word
block as required.
TBST TSIZ[0Ð3]
Negated 0 0 0 1
Negated 0 0 1 0
Negated 0 0 1 1
Negated 0 1 0 0
Negated 0 1 0 1
Negated 0 1 1 0
MOTOROLA
Table 8-3 Transfer Code Encoding
Read
Core data transaction
Core touch load
Core instruction fetch
Reserved
DMA function code 0
DMA function code 1
Table 8-4. Transfer Size Signal Encoding
Transfer Size
1 Byte Byte
2 Bytes Half-word
3 Bytes Ñ
4 Bytes Word
5 Bytes Extended 5 bytes
6 Bytes Extended 6 bytes
Chapter 8. The 60x Bus
Part III. The Hardware Interface
Write
Any write
Ñ
Ñ
Ñ
Reserved
Reserved
Comments Source
Core and DMA
Core and DMA
Core and DMA
Core and DMA
SDMA (MPC8260 only)
SDMA (MPC8260 only)
8-13