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Part III. The Hardware Interface
TDI
TRST
TMS
TCK
The TAP consists of the signals in Table 12-1.
Signal
TCK
A test clock input to synchronize the test logic.
TMS
A test mode select input (with an internal pull-up resistor) that is sampled on the rising edge of TCK to
sequence the TAP controllerÕs state machine.
TDI
A test data input (with an internal pull-up resistor) that is sampled on the rising edge of TCK.
TDO
A data output that can be three-stated and actively driven in the shift-IR and shift-DR controller states. TDO
changes on the falling edge of TCK.
TRST
An asynchronous reset with an internal pull-up resistor that provides initialization of the TAP controller and
other logic required by the standard.
12.2 TAP Controller
The TAP controller is responsible for interpreting the sequence of logical values on the
TMS signal. It is a synchronous state machine that controls the operation of the JTAG logic.
The value shown adjacent to each bubble represents the value of the TMS signal sampled
on the rising edge of the TCK signal. Figure 12-2 shows the state machine.
12-2
Boundary Scan Register
Bypass
Instruction Apply & Decode Register
3
2
4ÐBit Instruction Register
TAP Controller
Figure 12-1. Test Logic Block Diagram
Table 12-1. TAP Signals
Description
MPC8260 PowerQUICC II UserÕs Manual
M
U
X
1
0
M
U
TDO
X
MOTOROLA
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