Periodic Interrupt Timer Register (Pitr); Siu Pin Multiplexing - Motorola MPC8260 PowerQUICC II User Manual

Part II. ConÞguration and Reset
Table 4-22 describes PITC Þelds.
Bits Name
0Ð15 PITC Periodic interrupt timing count. Bits 0Ð15 are deÞned as the PITC, which contains the count for the
periodic timer. Setting PITC to 0xFFFF selects the maximum count period.
16Ð31 Ñ Reserved, should be cleared.

4.3.3.3 Periodic Interrupt Timer Register (PITR)

The periodic interrupt timer register (PITR), shown in Figure 4-40, is a read-only register
that shows the current value in the periodic interrupt down counter. The PITR counter is not
affected by reads or writes to it.
Bits 0 1 2
Field
Reset
R/W
Addr
Bits 16 17 18
Field
Reset
R/W
Addr
Figure 4-40. Periodic Interrupt Timer Register (PITR)
Table 4-23 describes PITR Þelds.
Bits Name
0Ð15 PITC Periodic interrupt timing count. Bits 0Ð15 are deÞned as the PIT. It contains the current count
remaining for the periodic timer. Writes have no effect on this Þeld.
16Ð31 Ñ Reserved, should be cleared.

4.4 SIU Pin Multiplexing

Some functions share pins. The actual pinout of the MPC8260 is shown in the hardware
speciÞcations. The control of the actual functionality used on a speciÞc pin is shown in
4-44
Table 4-22. PITC Field Descriptions
3 4 5 6
0000_0000_0000_0000
Read Only
19 20 21 22
0000_0000_0000_0000
Read Only
Table 4-23. PITR Field Descriptions
MPC8260 PowerQUICC II UserÕs Manual
Description
7 8 9 10
PIT
0x10248
23 24 25 26
Ñ
0x1024A
Description
11 12 13 14
27 28 29 30
MOTOROLA
15
31