C Master Write (Slave Read); C Loopback Testing; C Master Read (Slave Write) - Motorola MPC8260 PowerQUICC II User Manual

Part IV. Communications Processor Module
34.3.1 I 2

C Master Write (Slave Read)

If the MPC8260 is the master, prepare the transmit buffers and BDs before initiating a write.
Initialize the Þrst transmit data byte with the slave address and write request (R/W = 0).
If the MPC8260 is the slave target of the write, prepare receive buffers and BDs to await
the masterÕs request. Figure 34-4 shows the timing for a master write.
SDA
Note: Data and ACK are repeated n times.
A master write occurs as follows:
1. The master core sets I2COM[STR]. The transfer starts when the SDMA channel
loads the Tx FIFO with data and the I
2
2. The I C master generates a start conditionÑa high-to-low transition on SDA while
SCL is highÑand the transfer clock SCL pulses for each bit shifted out on SDA. If
the master transmitter detects a multiple-master collision (by sensing a Ô0Õ on SDA
while sending a Ô1Õ), transmission stops and the channel reverts to slave mode. A
maskable interrupt is sent to the masterÕs core so software can try to retransmit later.
3. The slave acknowledges each byte and writes to its current receive buffer until a new
start or stop condition is detected.
4. After sending each byte, the master monitors the acknowledge indication. If the
slave receiver fails to acknowledge a byte, transmission stops and the master
generates a stop conditionÑa low-to-high transition on SDA while SCL is high.
34.3.2 I 2

C Loopback Testing

When in master mode, an I
requests. The master I
(programmed in I2ADD). The masterÕs receiver monitors the transmission and reads the
transmitted data into its receive buffer. Loopback operation requires no special register
programming.
34.3.3 I

C Master Read (Slave Write)

2
Before initiating a master read with the MPC8260, prepare a transmit buffer of size n+1
bytes, where n is the number of bytes to be read from the slave. The Þrst transmit byte
should be initialized to the slave address with R/W = 1. The next n transmit bytes are used
strictly for timing and can be left uninitialized. ConÞgure suitable receive buffers and BDs
to receive the slaveÕs transmission.
34-4
S
T
A
R
T
W
Device Address
2
Figure 34-4. I C Master Write Timing
2
C controller supports loopback operation for master write
2
C controller simply issues a write request directed to its own address
MPC8260 PowerQUICC II UserÕs Manual
A A
C C
K K
Data Byte
2
C bus is not busy.
S
T
O
P
MOTOROLA