Smc Buffer Descriptor Operation - Motorola MPC8260 PowerQUICC II User Manual

Table 26-1. SMCMR1/SMCMR2 Field Descriptions (Continued)
Bits Name
10Ð11 SM SMC mode.
00 GCI or SCIT support.
01 Reserved.
10 UART (must be selected for SMC UART operation).
11 Totally transparent operation.
12Ð13 DM Diagnostic mode.
00 Normal operation.
01 Local loopback mode.
10 Echo mode.
11 Reserved.
14 TEN SMC transmit enable.
0 SMC transmitter disabled.
1 SMC transmitter enabled.
15 REN SMC receive enable.
0 SMC receiver disabled.
1 SMC receiver enabled.

26.2.2 SMC Buffer Descriptor Operation

In UART and transparent modes, the SMCÕs memory structure is like the SCCÕs, except that
SMC-associated data is stored in buffers. Each buffer is referenced by a BD and organized
in a BD table located in the dual-port RAM. See Figure 26-3.
Dual-Port RAM
SMC TxBD
Table
SMC RxBD
Table
Pointer to SMCx
RxBD Table
Pointer to SMCx
TxBD Table
MOTOROLA
Status and Control
Status and Control
Figure 26-3. SMC Memory Structure
Chapter 26. Serial Management Controllers (SMCs)
Part IV. Communications Processor Module
Description
TxBD Table
Data Length
Buffer Pointer
RxBD Table
Data Length
Buffer Pointer
External Memory
Tx Data Buffer
Rx Data Buffer
26-5