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7.2.4.4 Global (GBL)
The global (GBL) signal is an input/output signal on the MPC8260.
7.2.4.4.1 Global (GBL)ÑOutput
Following are the state meaning and timing comments for the GBL output signal.
State Meaning
Timing Comments Assertion/NegationÑSame as A[0Ð31].
7.2.4.4.2 Global (GBL)ÑInput
Following are the state meaning and timing comments for the GBL input signal.
State Meaning
Timing Comments Assertion/NegationÑSame as A[0Ð31].
7.2.4.5 Caching-Inhibited (CI)ÑOutput
The cache inhibit (CI) signal is an output signal on the MPC8260. Following are the state
meaning and timing comments for CI.
State Meaning
Timing Comments Assertion/NegationÑSame as A[0Ð31].
7.2.4.6 Write-Through (WT)ÑOutput
The write-through (WT) signal is an output signal on the MPC8260. Following are the state
meaning and timing comments for WT.
State Meaning
MOTOROLA
High ImpedanceÑSame as A[0Ð31].
AssertedÑIndicates that the transaction is global and should be
snooped by other devices. GBL reßects the M bit (WIM bits) from
the MMU except during certain transactions.
NegatedÑIndicates that the transaction is not global and should not
be snooped by other devices.
High ImpedanceÑSame as A[0Ð31].
AssertedÑIndicates that a transaction must be snooped by
MPC8260.
NegatedÑIndicates that a transaction should not be snooped by
MPC8260. (In addition, certain non-global transactions are snooped
for reservation coherency.)
AssertedÑIndicates that the transaction in progress should not be
cached. CI reßects the I bit (WIM bits) from the MMU except during
certain transactions.
NegatedÑIndicates that the transaction should be cached.
High ImpedanceÑSame as A[0Ð31].
AssertedÑIndicates that the transaction should operate in write-
through mode. WT reßects the W bit (WIM bits) from the MMU
except during certain transactions. WT may be asserted during read
transactions.
Chapter 7. 60x Signals
Part III. The Hardware Interface
7-9
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