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Part IV. Communications Processor Module
Data length represents the number of octets the CP should transmit from this buffer. It is
never modiÞed by the CP. The data length can be even or odd, but if the number of bits in
the transparent character is greater than 8, the data length should be even. For example, to
transmit three transparent 8-bit characters, the data length Þeld should be initialized to 3.
However, to transmit three transparent 9-bit characters, the data length Þeld should be
initialized to 6 because the three 9-bit characters occupy three half words in memory.
The data buffer pointer points to the Þrst byte of the buffer. They can be even or odd, unless
character length is greater than 8 bits, in which case the transmit buffer pointer must be
even. For instance, the pointer to 8-bit transparent characters can be even or odd, but the
pointer to 9-bit transparent characters must be even. The buffer can reside in internal or
external memory.
26.4.10 SMC Transparent Event Register (SMCE)/Mask Register
(SMCM)
The SMC event register (SMCE) generates interrupts and reports events recognized by the
SMC channel. When an event is recognized, the SMC sets the corresponding SMCE bit.
Interrupts are masked in the SMCM, which has the same format as the SMCE. SMCE bits
are cleared by writing a 1 (writing 0 has no effect). Unmasked bits must be cleared before
the CP clears the internal interrupt request.
Bit
0
Field
Reset
R/W
Address
0x11A86 (SMCE1), 0x11A96 (SMCE2)/ 0x11A8A (SMCM1), 0x11A9A (SMCM2)
Figure 26-14. SMC Transparent Event Register (SMCE)/Mask Register (SMCM)
Table 26-16 describes SMCE/SMCM Þelds.
Bits Name
0Ð2
Ñ
Reserved, should be cleared.
3
TXE
Tx error. Set when an underrun error occurs on the transmitter channel.
4
Ñ
Reserved, should be cleared.
5
BSY
Busy condition. Set when a character is received and discarded due to a lack of buffers. Reception
begins after a new buffer is provided. Executing an
wait for resynchronization.
6
TXB
Tx buffer. Set after a buffer is sent. If the L bit of the TxBD is set, TXB is set when the last character
starts being sent. A one character-time delay is required to ensure that data is completely sent over the
transmit signal. If the L bit of the TxBD is cleared, TXB is set when the last character is written to the
transmit FIFO. A two character-time delay is required to ensure that data is completely sent.
7
RXB
Rx buffer. Set when a buffer is received (after the last character is written) on the SMC channel and its
associated RxBD is now closed.
26-28
1
2
Ñ
Table 26-16. SMCE/SMCM Field Descriptions
MPC8260 PowerQUICC II UserÕs Manual
3
4
TXE
Ñ
BSY
0
R/W
Description
ENTER HUNT MODE
5
6
7
TXB
RXB
command makes the receiver
MOTOROLA
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