Motorola MPC8260 PowerQUICC II User Manual page 358

Part III. The Hardware Interface
MPC8260
A[19–28]
Figure 10-67. DRAM Interface Connection to the 60x Bus (64-Bit Port Size)
After timings are created, programming the UPM continues with translating these timings
into tables representing the RAM array contents for each possible cycle. When a table is
completed, the global parameters of the UPM must be deÞned for handling the disable
timer (precharge) and the refresh timer relative to Figure 10-67. Table 10-41 shows settings
of different Þelds.
Machine select UPMA
Port size 64-bit
No write protect (R/W)
Refresh timer value (1024 refresh cycles)
Refresh timer enable
Address multiplex size
Disable timer period
Select between GPL4 and Wait = GPL4 data sample at clock rising edge
Burst inhibit device
The OR and BR of the speciÞc bank must be initialized according to the address mapping
of the DRAM device used. The MS Þeld should indicate the speciÞc UPM selected to
handle the cycle. The RAM array of the UPM can than be written through use of the
10-82
BS[0–7]
CS1
BCTL0
D[0–63]
Table 10-41. UPMs Attributes Example
Explanation
MPC8260 PowerQUICC II UserÕs Manual
1M x 16
RAS
CAS[0–1]
W
A[0–9]
D[0–15]
16
16
D[0–15]
RAS
CAS[0–1]
W
A[0–9]
1M x 16
BRx[MS]
BRx[PS]
BRx[WP]
PURT[PURT]
MxMR[RFEN]
MxMR[AMx]
MxMR[DSx]
MxMR[GPL_x4DIS]
ORx[BI]
1M x 16
RAS
CAS[0–1]
W
A[0–9]
D[0–15
16
16
D[0–15]
RAS
CAS[0–1]
W
A[0–9]
1M x 16
Field Value
0b100
0b00
0b0
0x0C
0b1
0b010
0b01
0b0
0b0
MOTOROLA