Sun Oracle SPARC T3-2 Service Manual page 65

Warning messages use the following syntax:
WARNING: message
Informational messages use the following syntax:
INFO: message
In the following example, POST reports an uncorrectable memory error affecting
DIMM locations /SYS/MB/CMP0/MR0/B0B0/CH0/D0 and
/SYS/MB/CMP0/B0B1/CH0/D0. The error was detected by POST running on node
0, core 7, strand 2.
2010-07-03 18:44:13.359 0:7:2>Decode of Disrupting Error Status Reg
(DESR HW Corrected)
2010-07-03 18:44:13.517 0:7:2>
(non-local) sw_recoverable_error.
2010-07-03 18:44:13.638 0:7:2>
(non-local) hw_corrected_and_cleared_error.
2010-07-03 18:44:13.773 0:7:2>
2010-07-03 18:44:13.836 0:7:2>Decode of NCU Error Status Reg bits
00000000.22000000
2010-07-03 18:44:13.958 0:7:2>
a Software Recoverable Error Request
2010-07-03 18:44:14.095 0:7:2>
issued a Hardware Corrected-and-Cleared Error Request
2010-07-03 18:44:14.248 0:7:2>
2010-07-03 18:44:14.296 0:7:2>Decode of Mem Error Status Reg Branch 1
bits 33044000.00000000
2010-07-03 18:44:14.427 0:7:2>
on an UE if VEU = 1, or VEF = 1, or higher priority error in same cycle.
2010-07-03 18:44:14.614 0:7:2>
on a CE if VEC = 1, or VEU = 1, or VEF = 1, or another error in same cycle.
2010-07-03 18:44:14.804 0:7:2>
on an UE, if VEF = 0 and no fatal error is detected in same cycle.
2010-07-03 18:44:14.983 0:7:2>
on a CE, if VEF = VEU = 0 and no fatal or UE is detected in same cycle.
2010-07-03 18:44:15.169 0:7:2>
if the error was a DRAM access UE.
2010-07-03 18:44:15.304 0:7:2>
if the error was a DRAM access CE.
2010-07-03 18:44:15.440 0:7:2>
2010-07-03 18:44:15.486 0:7:2>
1 = 00000034.8647d2e0
2010-07-03 18:44:15.614 0:7:2>
00000005.d21bc0c0
2010-07-03 18:44:15.715 0:7:2>
bits 00300000.00000000
1
1
1
1
1
1
1
1
1
1
DRAM Error Address Reg for Branch
DRAM Error Location Reg for Branch
DESR_SOCSRE:
DESR_SOCHCCE:
NESR_MCU1SRE:
NESR_MCU1HCCE:
MEU 61 R/W1C Set to 1
MEC 60 R/W1C Set to 1
VEU 57 R/W1C Set to 1
VEC 56 R/W1C Set to 1
DAU 50 R/W1C Set to 1
DAC 46 R/W1C Set to 1
Physical Address is
Detecting and Managing Faults
SOC
SOC
MCU1 issued
MCU1
53