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Assignment Of System Interrupts To The Apic Local Unit; Floating Point Exception Interrupt; Apic Memory Mapping - Intel MultiProcessor Specification

Intel multiprocessor specification
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MultiProcessor Specification
3.6.3

Assignment of System Interrupts to the APIC Local Unit

The APIC local unit has two general-purpose interrupt inputs, which are reserved for system
interrupts. These interrupt inputs can be individually programmed to different operating modes.
Like the I/O APIC interrupt lines, the local APIC interrupt line assignments of a non-PC/AT-
compatible system are system implementation specific. Refer to Chapter 4 for custom
implementations and to Chapter 5 for default configurations.
3.6.4

Floating Point Exception Interrupt

For PC/AT compatibility, the bootstrap processor must support DOS-compatible FPU execution
and exception handling while running in either of the PC/AT-compatible modes.
floating point error signals from the BSP must be routed to the interrupt request 13 signal, IRQ13,
when the system is in PIC or virtual wire mode. While floating point error signals from an
application processor need not be routed to IRQ13, platform designers may choose to connect the
two. For example, connecting the floating point error signal from application processors to IRQ13
can be useful in the case of a platform that supports dynamic choice of BSP during boot.
In
symmetric
mode, a compliant system supports only on-chip floating point units, with error
signaling via interrupt vector 16.
floating point exceptions when the system is in symmetric mode.
It is recommended that hardware platforms be designed to block delivery of floating point
exception signals from the processors once the system has switched into symmetric mode to avoid
delivery of superfluous interrupts. If done, such blocking must be implemented in a manner that is
transparent to the operating system. However, the operating system must still be prepared to
handle interrupts generated through assertion of floating point error signals, because on some
platforms these signals may still be routed to IRQ13 even after the switch to symmetric mode.
3.6.5

APIC Memory Mapping

In a compliant system, all APICs must be implemented as memory-mapped I/O devices. APIC
base addresses are at the top of the memory address space. All APIC local units are mapped to the
same addresses, which are not shared. Each processor accesses its local APIC via these memory
addresses. The default base address for the local APICs is 0FEE0_0000h.
Unlike the local APICs, the I/O APICs are mapped to give shared access from all processors,
providing full symmetric I/O access. The default base address for the first I/O APIC is
0FEC0_0000h. Subsequent I/O APIC addresses are assigned in 4K increments. For example, the
second I/O APIC is at 0FEC0_1000h.
Non-default APIC base addresses can be used if the MP configuration table is provided. (Refer to
Chapter 4.) However, the local APIC base address must be aligned on a 4K boundary, and the I/O
APIC base address must be aligned on a 1K boundary.
3-12
Operating systems must use interrupt vector 16 to manage
This means that
Version 1.4

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