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7.2.6.
Deep Sleep State — 6
The Deep Sleep state is the lowest power state the processor can enter while maintaining
context. The Deep Sleep state is entered by stopping the BCLK input (after the Sleep state
was entered from the assertion of the SLP# pin). The processor is in Deep Sleep state
immediately after the BCLK is stopped. It is recommended that the BCLK input be held low
during the Deep Sleep state. Stopping of the BCLK input lowers the overall current
consumption to leakage levels.
To re-enter the Sleep state, the BCLK input must be restarted. A period of 1 ms (to allow for
PLL stabilization) must occur before the processor can be considered to be in the Sleep state.
While in Deep Sleep state, the processor is incapable of responding to snoop transactions or
latching interrupt signals. No transitions or assertions of signals are allowed on the system
bus while the processor is in Deep Sleep state. Any transition on an input signal before the
processor has returned to Stop-Grant state will result in unpredictable behavior.
7.2.7.
Clock Control and Low Power Modes
The processor provides the clock signal to the L2 cache. During AutoHALT Power Down
and Stop-Grant states, the processor will process a system bus snoop. The processor will not
stop the clock data to the L2 cache during AutoHALT Power Down or Stop-Grant states.
Entrance into the HALT/Grant Snoop state will allow the L2 cache to be snooped, similar to
Normal state.
When the processor is in Sleep and Deep Sleep states, it will not respond to interrupts or
snoop transactions. During Sleep state, the clock to the L2 cache is not stopped. During the
Deep Sleep state, the clock to the L2 cache is stopped. The clock to the L2 cache will be
restarted only after the internal clocking mechanism for the processor is stable (i.e., the
processor has re-entered Sleep state).
The PICCLK should not be removed during the AutoHALT Power Down or Stop-Grant
states. The PICCLK can be removed during the Sleep or Deep Sleep states. When
transitioning from the Deep Sleep to Sleep states, the PICCLK must be restarted with the
BCLK.
7.3.
POWER AND GROUND PINS
The operating voltage of the processor core and of the L2 cache die differ from each other.
There are two groups of power inputs on the Pentium II processor package to support the
voltage difference between the two components in the package. There are also five pins
defined on the package for voltage identification (VID). These pins specify the voltage
required by the processor core. These have been added to cleanly support voltage
specification variations on current and future Pentium II processors.
For clean on-chip power distribution, Pentium II processors have 27 V
(ground) inputs. The 27 V
pins are further divided to provide the different voltage levels to
CC
ELECTRICAL SPECIFICATIONS
(power) and 30 V
CC
SS
7-5
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