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Intel® 80331 I/O Processor Design Guide
Memory Controller
Table 69.
DDR II 400 Embedded Clock (PLL) Lengths
Traces
Description
TL0
Breakout
TL1
Lead-in
For
TL2
Termination
TL0_PLLFB
PLL Feedback
TL1_PLLFB
For
TL2_PLLFB
Termination
TL0_sdram
TL1_sdram
For
TL2_sdram
Termination
TL0_reg
TL1_reg
For
TL2_reg
Termination
114
Minimum
Maximum
Layer
Length
Length
Any
0"
0.5"
Microstrip/Str
2 "
10"
ipline
Microstrip
0"
.1"
Microstrip or
2.2 "
2.3"
stripline
Microstrip or
20 mils
50 mils
stripline
Microstrip or
0"
100 mils
stripline
Microstrip/Str
2.7"
2.75"
ipline
Microstrip/Str
0.5"
0.75"
ipline
Microstrip/Str
0"
150mils
ipline
Microstrip/Str
2"
2.25"
ipline
Microstrip/Str
25 mils
50mils
ipline
Microstrip/Str
100 mils
125 mils
ipline
Trace
Spacing
Impedance
5 mils
Differential
20 mils
impedance of
from
100 ohms +/-
others
15%
5 mils
Same as TL1
20 mils
20 mils
5 mils
20 mils
Same as TL1
from
others
20 mils
from
others
5 mils
Same as TL1
20 mils
20 mils
5 mils
Notes
5 mils trace width OK for
breakout.
• Route as differential pair.
Refer to table __ for details
Route as per DDRII JEDEC
Route as per DDRII JEDEC
Route as per DDRII JEDEC
Route as per DDRII JEDEC
Route as per DDRII JEDEC
Route as per DDRII JEDEC
Route as per DDRII JEDEC
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