Pci 33 Mhz Mixed Topology; Pci 33 Mhz Mixed Mode Routing Topology; Pci 33 Mhz Mixed Mode Routing Recommendations - Intel 80331 Design Manual

Table 25. PCI 33 MHz Embedded Routing Recommendations (Sheet 2 of 2)
Group Spacing
Trace Length 1 TL1: From
80331 signal Ball to first
junction
Trace Length TL2 to TL4
between junctions
Trace Length TL_EM1 to
TL_EM8 junction to
embedded devices
Length Matching
Requirements:
Number of vias
6.4.19

PCI 33 MHz Mixed Topology

Figure 34
design with slots.
Figure 34.

PCI 33 MHz Mixed Mode Routing Topology

Table 26. PCI 33 MHz Mixed Mode Routing Recommendations (Sheet 1 of 2)
Reference Plane
Breakout
Motherboard Trace Impedance (microstrip and
stripline)
Add-in card Impedance (microstrip and
stripline)
Stripline Trace Spacing
Microstrip Trace Spacing
Group Spacing
Spacing from other groups: 25 mils minimum edge-to-edge
4.5" maximum
1.5" minimum - 3.0" maximum
2.0" minimum - 3.0" maximum
No length matching is required among datalines. For length matching for clocks,
refer clock guidelines
Four vias maximum
and Table 26 provides routing details for a topology with for an embedded PCI 33 MHz
EM1
TL1
EM2
Parameter
Intel® 80331 I/O Processor Design Guide
Table 8.
AD1
AD2
CONN1
CONN2
TL3 TL4
Routing Guideline for lower AD
Bus
Route over an unbroken ground plane
5 mils on 5 mils spacing. Maximum length of the breakout is
500 mils.
50 Ohms +/- 15%
57 Ohms +/- 15%
10 mils, from edge to edge
15 mils, from edge to edge
Spacing from other groups: 25 mils minimum edge-to-edge
PCI-X Layout Guidelines
AD3 AD4
CONN3 CONN4
TL5
Routing Guideline for
upper AD Bus
65