Figure 46.
Embedded DDR 333 Unbuffered Clock Topology
Table 50.
Embedded DDR 333 Unbuffered Clock Topology Lengths
Traces
Description
TL0
Lead-in
TL1
TL2
TL3
TL4
Breakout
22 ohms
+/- 5%
TL4
22 ohms
+/- 5%
Minimum
Maximum
Layer
Length
Length
Microstrip/
2"
10"
Stripline
0.47"
0.49"
0.72 "
0.73"
0.36
0.37"
Any
0.5"
Intel® 80331 I/O Processor Design Guide
120 ohms
+/-5%
TL0
TL1
Trace
Spacing
Impedance
20 mils
Differential 100
from any
ohms +/- 15%
other
signals
Same as TL0
20 mils
Same as TL0
20 mils
Same as TL0
20 mils
5 mils
Memory Controller
TL3
TL3
TL2
TL3
TL2
TL3
TL2
TL3
TL3
Notes
• Match within +/- 1" of
strobes (DQS) from
controller to SDRAM and
within +/- 1" of
Address/CMD control from
controller to SDRAM input.
• Route as T Differential
pairs as per DDR1 DIMM
JEDEC.
Route per DDR1 JEDEC
Route per DDR1 JEDEC
Route per DDR1 JEDEC
Route as differential
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
SDRAM
95