Intel 80331 Design Manual page 9

Intel® 80331 I/O Processor Design Guide
Contents
49 Embedded DDR 333 Buffered Clock Topology Lengths ............................................................94
50 Embedded DDR 333 Unbuffered Clock Topology Lengths ........................................................95
51 DDR 333 Embedded Address/Command Routing Recommendations ......................................96
52 Embedded DDR 333 Unbuffered Address/CMD Topology Lengths...........................................98
53 Embedded DDR 333 Registered Address/CMD Topology Lengths ...........................................99
54 x64 DDR Memory Configuration...............................................................................................101
55 x72 DDR Memory Configuration...............................................................................................101
56 DDR II Topologies Simulated ...................................................................................................102
57 Example Topology for DDRII Trace Width/Impedance Requirements .....................................103
58 DDRII 400 DIMM Source Synchronous Routing Recommendations........................................105
60 DDR II 400 DIMM DQS Lengths...............................................................................................106
59 DDR II 400 DIMM DQ Lengths .................................................................................................106
61 DDRII 400 DIMM Clock Routing Recommendations ................................................................107
62 DDR II 400 DIMM Clock Lengths..............................................................................................107
63 DDRII 400 DIMM Address/Command/Control Routing Recommendation ...............................108
64 DDR II 400 DIMM Address/CMD Lengths ................................................................................109
65 DDRII 400 Embedded Source Synchronous Routing Recommendations................................110
66 DDR II 400 Embedded DQ Lengths .........................................................................................111
67 DDR II 400 Embedded DQS Lengths .......................................................................................112
68 DDRII 400 Embedded Clock Routing Recommendations ........................................................113
69 DDR II 400 Embedded Clock (PLL) Lengths ............................................................................114
70 DDRII 400 Embedded Address/Command/Control Routing Recommendations......................116
71 DDR II 400 Embedded Address/CMD Lengths ........................................................................117
72 Flash Wait State Profile Programming .....................................................................................125
73 Routing Guideline Bidirectional Single Load.............................................................................127
74 Routing Guideline Latched Bidirectional Latch Single Load .....................................................128
75 Routing Guideline Latch Bidirectional Two Loads ....................................................................129
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76 Intel 80331 I/O Processor Bias Voltages ...............................................................................131
77 Four Peaks Customer Reference Board Features ...................................................................138
78 Logic Analyzer Pod 1................................................................................................................143
80 Logic Analyzer Pod 3................................................................................................................144
79 Logic Analyzer Pod 2................................................................................................................144
82 Logic Analyzer Pod 5................................................................................................................145
81 Logic Analyzer Pod 4................................................................................................................145
83 Logic Analyzer Pod 6................................................................................................................146
84 Design References ...................................................................................................................147
85 Intel Related Documentation ....................................................................................................147
86 Electronic Information ...............................................................................................................148
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