Pci 66 Mhz Embedded Topology; Pci 66 Mhz Embedded Table - Intel 80331 Design Manual

Table 21. PCI 66 MHz Slot Table (Sheet 2 of 2)
Trace Length TL_AD1, TL_AD2 from connector to
receiver
Length Matching Requirements
Number of Vias
6.4.15

PCI 66 MHz Embedded Topology

Figure 30
design.
Figure 30.

PCI 66 MHz Embedded Topology

Table 22. PCI 66 MHz Embedded Table (Sheet 1 of 2)
Reference Plane
Breakout
Motherboard Trace Impedance (microstrip and
stripline)
Add-in card Impedance (microstrip and stripline)
Stripline Trace Spacing
Microstrip Trace Spacing
Group Spacing
Parameter
and Table 22 provides routing details for a topology with for an embedded PCI 66 MHz
Parameter
Intel® 80331 I/O Processor Design Guide
Routing Guideline for AD
Bus
0.75" minimum - 1.5"
maximum
No length matching is required among datalines. For
length matching for clocks, refer clock guidelines
Table 8.
Four vias maximum
EM 1
TL 1 T L2
EM 2
Routing Guideline for AD Bus
Route over an unbroken ground plane
5 mils on 5 mils spacing. Maximum length of the
breakout is 500 mils.
50 Ohms +/- 15%
60 Ohms +/- 15%
10 mils, from edge to edge
15 mils, from edge to edge
Spacing from other groups: 25 mils minimum edge to
edge
PCI-X Layout Guidelines
Routing Guideline for
Upper AD Bus
1.75" minimum - 2.75"
maximum
E M 3
E M 4
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