Routing Guideline Latched Bidirectional Latch Single Load; Peripheral Bus Latched Bidirectional Single Load Topology - Intel 80331 Design Manual

I/o processor
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Intel® 80331 I/O Processor Design Guide
Peripheral Local Bus
Figure 65.

Peripheral Bus Latched Bidirectional Single Load Topology

Table 74.

Routing Guideline Latched Bidirectional Latch Single Load

Reference Plane
Breakout
Routing
Motherboard Impedance (for both microstrip and
stripline)
Add-in card Impedance (for both microstrip and
stripline)
Trace Spacing (center to center)
Trace Length TL1
Trace Length to TL2
Trace Length to strapping resistors
Routing Recommendations
128
T L1
Parameter
Flash
Latch
Routing Guidelines
Route over unbroken ground plane or power plane. If
routing over power plane maintain this consistency
throughout the topology.
5 mils on 5 mils spacing. Maximum length of breakout
region is 500mils.
Microstrip or stripline or combination of microstip and
stripline.
50 ohms +/- 15%
60 ohms +/- 15%
• > 12 mils between all AD lines
• > 20 mils must be maintained from all other
signals or vias.
2.0" to 10.0"
0.5" to 2.0"
0.5" to 3.0" from the last device on the bus.
Number of vias for microstrip < 2
Number of vias for stripline < 4
Route as daisy-chain only.
Address latches for 16 bit implementations may be in
any of the device locations for ease of routing.

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