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Table 53.
Embedded DDR 333 Registered Address/CMD Topology Lengths
Traces
Description
TL1
Breakout
TL2
TL3
TL4
TL5
TL6
TL7
TL8
TL9
Lead-in
TL10
TL11
Vtt
NOTES:
1. Post Register recommendations are referenced from JEDEC DDR1 Registered DIMM.
2. TL2 to TL8 are numbered JEDEC references.
Minimum
Maximum
Layer
Length
Length
Microstrip/
0"
0.5"
Strip
Microstrip
0.6 "
1.37"
1.39"
2.57"
0.4"
0.56"
0.14"
0.15"
0.48"
0.63"
0.20"
0.32"
0.49
0.72"
Microstrip
1"
9"
Microstrip
-
0.2"
Microstrip
0.25'
0.5"
Intel® 80331 I/O Processor Design Guide
Trace
Spacing
Impedance
5 mils
45 ohms+/-15%
or 50 ohms
12 mils
+/-15%
Same as TL2
12 mils
Same as TL2
12 mils
Same as TL2
12 mils
Same as TL2
12 mils
Same as TL2
12 mils
Same as TL2
12 mils
45 ohms+/-15%
or 50 ohms
12 mils
+/-15%
Same as TL2
12 mils
5 mils
Memory Controller
Notes
5 mils trace width for breakout
Spacing: within the same
group 12 mils
Other groups 20 mils
Spacing: within the same
group 12 mils
With other groups 20 mils
5 mils trace width OK for
breakout
99
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