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Table 17.
Combination of Slot and Embedded PCI-X 100 MHz Routing 2 Recommendations
(Sheet 2 of 2)
Trace Length TL_AD1,
TL_AD2 - from connector to
receiver
Length Matching
Requirements:
Number of vias
6.4.11
PCI-X 66 MHz Slot Topology
Figure 26
66 MHz application.
Figure 26.
PCI-X 66 MHz Slot Routing Topology
Table 18.
PCI-X 66 MHz Slot Routing Recommendations (Sheet 1 of 2)
Parameter
Reference Plane
Breakout
Motherboard Trace
Impedance (microstrip and
stripline)
Add-in card Impedance
(microstrip and stripline)
Stripline Trace Spacing
Microstrip Trace Spacing
Group Spacing
Trace Length 1 (TL1): From
80331 signal Ball to first
junction
Trace Length TL2 to TL4
between junctions
0.75" minimum - 1.5" maximum
No length matching is required among datalines. For length matching for clocks,
refer clock guidelines
Three vias maximum
and
Table 18
provides routing details for a topology with for an embedded PCI-X
A D 1
C O N N 1
T L 1
Routing Guideline for AD Bus
Route over an unbroken ground plane
5 mils on 5 mils spacing. Maximum length of the breakout is 500 mils.
50 Ohms +/- 15%
57 Ohms +/- 15%
12 mils, from edge to edge
18 mils, from edge to edge
Spacing from other groups: 25 mils minimum center to center
1.0" minimum - 6.0" maximum
0.8" minimum - 1.2" maximum
Intel® 80331 I/O Processor Design Guide
1.75" minimum - 2.75" maximum
Table
8.
A D 2
C O N N 2
T L 2
T L 3
1.0" minimum - 4.75" maximum
PCI-X Layout Guidelines
A D 3
A D 4
C O N N 3
C O N N 4
T L 4
57
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