Ddr 333 Unbuffered Dimm Clock Topology - Intel 80331 Design Manual

Intel® 80331 I/O Processor Design Guide
Memory Controller
Table 42. DDR 333 Unbuffered DIMM Clock Topology Lengths
Traces Description
TL1
(all 3
Breakout
clock
pairs)
TL2
(all 3 x
Lead-in
clock
pairs)
NOTE: Length matching should be done from die to DIMM connector
1. Between intra pairs +/- 25 mils
2. Between clock pairs M_CK0, M_CK1, M_CK2 +/- 100mils on unbuffered clocks
3. DQS lengths are within +/- 1.5 " max. of MCK for stripline
4. DQS lengths are within +/- 1.0 " max. of MCK for stripline
5. Address/Command/Control lengths are with-in 2" to 3" less than MCK
6. Any address/command/control lengths greater than M_CK from die to DIMM is not guaranteed for x2 bank
unbuffered configurations.
Figure 41.

DDR 333 Unbuffered DIMM Clock Topology

84
Minimum Maximum
Layer
Length Length
Microstrip 0.5"
Microstrip/
2 " 10"
Stripline
TL1_CK0
22 ohms +/- 5%
22 ohms +/- 5%
Clock Pair CK0
TL1_CK1
22 ohms +/- 5%
22 ohms +/- 5%
Clock Pair CK1
TL1_CK2
22 ohms +/- 5%
22 ohms +/- 5%
Trace
Spacing
Impedance
5 mils
Differential 20 mils
Impedance 100 from
ohms +/- 15% others
TL2_CK0
TL2_CK1
TL2_CK2
Clock Pair CK2
Notes
5 mils trace width OK for
breakout.
• Route as differential pairs.
• Series termination of 22
ohms +/- 5%.
184 pin DIMM Connector
Pins 137 & 138
184 pin DIMM Connector
Pins 16 & 17
184 pin DIMM Connector
Pins 76 & 75