Ddr Ii 400 Embedded Dq Lengths; Ddr Ii 400 Embedded Dq Topology - Intel 80331 Design Manual

Table 66.

DDR II 400 Embedded DQ Lengths

Traces Description
TL0 Breakout
TL1 Lead-in*
TL2
TL3
TL4 Same as TL1 Stripline
NOTES:
1. TL1 and TL4 are approximately the same length allowing Rs in the middle of the lead-in trace between the
controller and SDRAM.
2. Then controller to SDRAM lead-in traces are less than 6" the series resistor may be places anywhere in
between the center of the lead-in trace to SDRAM
Figure 55.

DDR II 400 Embedded DQ Topology

Minimum Maximum
Layer
Length Length
Microstrip 0" 0.5"
Stripline 1 " 4"
Microstrip 0" 0.1"
Microstrip 0" 0.1"
1" 4"
TL0 TL1
Intel® 80331 I/O Processor Design Guide
Trace
Spacing
Impedance
5 mils
45 ohms or 50
12 mils
ohms
5 mils
5 mils
45 ohms or 50
12 mils
ohms
22 Ohms +/-
5%**
TL2 Rs
Memory Controller
Notes
5 mils trace width OK for
breakout.
45 ohms +/- 15%
50 ohms +/- 15%
5 mils trace width OK for
termination fan out
5 mils trace width OK for
termination fan out
45 ohms +/- 15%
50 ohms +/- 15%
TL3 TL4
SDRAM
111