Intel ® 80331 I/O Processor Pci/X Layout Analysis - Intel 80331 Design Manual

Intel® 80331 I/O Processor Design Guide
PCI-X Layout Guidelines
®
6.4 Intel
The following sections describe layout recommendations based on the signal integrity simulation
analysis. This analysis was conducted using the following parameters:
•
System board stack up: 50 ohm +/- 15% single-ended impedance
•
Add-in card stack up: 60 ohm +/- 15% single-ended impedance
•
Driver Model 80331 IBIS
•
Receiver Model: generic models for PCI-X and PCI
•
Driver Package Model: 80331 model
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Connector Model: Multiline coupled model
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Generic Spec Models: PCI-X and PCI
•
Cross talk impact on timing was modeled
•
Process corners for PCB stack and trace geometries were modeled
•
PVT corner cases for buffers and package models were modeled
•
Signal quality analysis covered rise time at the receiver, fall time at the receiver, rising flight
time, falling flight time, low to high ring-back (noise margin high), high to low ringback (noise
margin low) and low and high overshoot.
Note: The overshoot and undershoot exceeded the specifications. The requirement calls for 0.5 V and the
observed overshoot in simulation was 1.2 V. This fact needs to be taken into consideration when
accessing the reliability of your application.
The following notes should be considered when designing to this section's design guide
recommendations:
1. The lengths recommended for AD lines are given as a range of length (for example 2.0" to
5.0"). This means that each AD bit can be routed any where between this range. There is no
length matching required among AD bits. For example, AD1 can be 2.0" and AD2 can be
5.0". Routing anywhere in this range assures that the bit will meet the Set up and Hold time
requirement. This is because each bit is sampled with respect to a common clock, independent
of its relation with other bits.
2. There is no length matching requirement between Clock and AD bits. This means, that the
clock can be routed to 6" and any AD bit can be 2". However the length matching requirement
among clocks to each devices (and feedback clock) remains.
3. If your board aligns to the topology in these recommendations with the exception of one or
more devices, these requirements listed are still valid. Each of the recommendations is made
with an assumption that any device can be a "no mount". In this case adding the length before
and after the "no mount" device, as a single segment is acceptable.
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80331 I/O Processor PCI/X Layout Analysis