Ddrii 400 Dimm Source Synchronous Routing Recommendations - Intel 80331 Design Manual

Table 58.

DDRII 400 DIMM Source Synchronous Routing Recommendations

Reference Plane
Layer
Breakout
Stripline Trace Impedance
Motherboard/Add-in Card Differential DQ
Stripline Trace Impedance
Motherboard/Add-in Card Differential DQS
DQ Group Spacing (edge to edge)
Overall Trace Length: 80331 signal Ball to DIMM
connector (no series connector)
DQS Length Matching:
• Trace Length Matching within DQS group
• Within one DQS pair plus and minus
• All DQ/DQS lines with respect to the clock signal
Number of Vias
Routing Guideline
Parameter
Intel® 80331 I/O Processor Design Guide
Routing Guideline
Route over unbroken ground plane
Strip line (layer 3 or layer 6)
5 mils on 5 mils spacing. Maximum length of breakout
region can be up to 500 mils either microstrip or strip
line
• DQ signals: Single ended strip lines at 45 ohm
+/15% or 50 ohms +/- 15% impedance. Refer
Table 57 and DIMM DQ topologies.
• DQS Signals: Differential ended strip lines at
100ohm impedance. Refer to
DQS Topologies.
• Spacing same group: 12 mils minimum
• Spacing from other DQ groups 20 mils minimum
• For DQS from any other signals: 20 mils minimum
2" minimum to 8" maximum (correlated with the clock
length from ball to DIMM).
+/-0.05" within DQS group
+/- 0.0250"
+/- 1" (target motherboard clock = +/- 1" of any
DQ/DQS pair)
Two (for differential signals the number of vias on +
and - signals must be the same)
Route all data signals and their associated strobes on
the same layer.
Memory Controller
Table 57 and DIMM
105