Trace Impedance - Intel 80331 Design Manual

Intel® 80331 I/O Processor Design Guide
Routing Guidelines
4.5

Trace Impedance

All signal layers require controlled impedance of 50 Ω +/- 15%, microstrip or stripline where
appropriate for motherboard applications and 60 Ω +/- 15%, microstrip or stripline, for add-in card
applications. Selecting the appropriate board stack-up to minimize impedance variations is very
important. When calculating flight times, it is important to consider the minimum and maximum
trace impedance based on the switching neighboring traces. Use wider spaces between traces, since
this can minimize trace-to-trace coupling, and reduce cross talk.
When a different stack up is used the trace widths must be adjusted appropriately. When wider
traces are used, the trace spacing must be adjusted accordingly (linearly).
It is highly recommended that a 2D Field Solver be used to design the high-speed traces. The
following Impedance Calculator URL provide approximations for the trace impedance of various
topologies. They may be used to generate the starting point for a full 2D Field solver.
http://emclab.umr.edu/pcbtlc/
The following website link provides a useful basic guideline for calculating trace parameters:
http://www.ultracad.com/calc.htm
Note: Using stripline transmission lines may give better results than microstrip. This is due to the
difficulty of precisely controlling the dielectric constant of the solder mask, and the difficulty in
limiting the plated thickness of microstrip conductors, which can substantially increase cross-talk.
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