Bus Width - Intel 80331 Design Manual

Intel® 80331 I/O Processor Design Guide
Peripheral Local Bus
8.1.3

Bus Width

Each address range attributes are programmed in the PBIs boundary registers. The PBI allows an
8-, or 16-bit data bus width for each range. The PBI places 8- and 16-bit data on low-order data
signals, simplifying the interface to narrow bus external devices. As shown in
is placed on lines AD[7:0]; 16-bit data is placed on lines AD[15:0].
Figure 62. Data Width and Low Order Address Lines
Flash memories need to be wired up in a manner consistent with the programmed bus width:
•
8-bit region: A[1:0] provide the demultiplexed byte address for a read burst.
•
16-bit region: A[2:1] provide the demultiplexed short-word address for a read burst.
Note: When using a 16 bit flash device mode A0 is a "don't care".
During initialization, bus width is selected for each of the two address ranges in the Peripheral Base
Address Registers (PBBAR0 - PBBAR1). In addition, the PBBAR0-PBBAR5 can be used to
configure these ranges as Peripheral Windows and to set a Wait state profile.
The PBI drives determinate values on all address/data signals during T
For an 8-bit bus, the PBI continues to drive address on unused data signals AD[15:8].
124
AD[15:8]
AD[7:0]
8 - Bit
A1
A0
A0
A1
A[2:0]
16 - Bit
A2
A1
A1
A2
/T
W D
Figure 62, 8-bit data
write operation states.