Embedded Ddr 333 Dq/Dqs Topology; Embedded Ddr 333 Dq/Dqs Topology Lengths - Intel 80331 Design Manual

Figure 44.

Embedded DDR 333 DQ/DQS Topology

Table 47.

Embedded DDR 333 DQ/DQS Topology Lengths

Traces Description
TL1 Breakout
TL2 Lead-in
TL3
TL4
VTT or Split
TL5
Termination
Same as
TL6
TL2
Notes:
1. Series termination is recommended in the center of the lead-in length
2. Parallel termination with single VTT Termination is preferred than split termination
3. For single VTT termination (preferred) the resistor value = 51 ohms +/- 5%
4. For split termination, the value of the resistors are 100 ohms +/- 5% to 2.5V and 100 ohms +/-
5% to Ground.
TL1
TL2
TL3
Minimum
Layer
Length
Microstrip/
0"
Stripline
Stripline 1 "
Microstrip 0"
Microstrip 0"
Microstrip 0.25"
Stripline 1"
Intel® 80331 I/O Processor Design Guide
TL5
22 ohms
TL4
+/- 5%
Maximum Trace
Spacing
Length Impedance
0.5" - 5 mils
45 ohms +/-
15% or 50
4" 12 mils
ohms +/-
15%
0.1" - 5 mils
0.1" - 5 mils
0.5" - 5 mils
Same as
4" 12 mils
TL2
Memory Controller
VTT
Rp
51 ohms
+/- 5%
TL6
SDRAM
Notes
5 mil trace width
breakout OK
• WIthin the same
group >12 mils
• Any other groups
(DQ/DQS/Clock) >20
mils
Fan out for series
termination
Fan out for series
termination
Single VTT
termination in VTT
island is preferred
Same as TL2
91