Ddr 333 Embedded Registered/Unbuffered Clock Routing Recommendations - Intel 80331 Design Manual

Table 48.

DDR 333 Embedded Registered/Unbuffered Clock Routing Recommendations

Reference Plane
Preferred Topology
Breakout Termination, Fan-in and Fanout width and
spacing
Trace Impedance
Trace Spacing (trace edge to edge)
Registered Termination
Un-buffered Termination
Length matching Requirements:
• Within Differential Clock pairs
• Registered Clock from IOP Die to PLL Input with
Respect to DQS
• Registered Clock from IOP Die to PLL Input with
Respect to Add/CMD/Control
• Un-buffered Clock from IOP Die to SDRAM input
with respect to DQS
• Un-buffered Clock from IOP Die to SDRAM input
with respect to Add/CMD/Control
• Unbuffered Clock Pairs
Number of vias
Routing Guideline
Parameter
Intel® 80331 I/O Processor Design Guide
Routing Guideline
• Route over unbroken ground plane
• Stripline routing is recommended for the clock
signals. Micro-strip will work with strict adherence
to all routing recommendations. Careful
simulation and timing analysis of ADD/CMD
signals is recommended.
5 mils x 5 mils. Microstrip is recommended for pin
escapes and terminations.
Differential Target impedance of 100 Ohms +/-15%
(Applies to both Buffered and Unbuffered Topologies)
5 mils. for breakout region
>20 mils. between any other signals or vias including
other clock pairs.
None required
• 22 ohms +/-5% series termination on each
differential leg after breakout route
• Post PLL and Unbuffered SDRAM Clock areas to
be Routed as T Point differential as per JEDEC
Unbuffered and Registered Post PLL Clock
Topology
• The package lengths from Die to Ball provided in
Table 37 must be accounted for when length
matching.
• See respective registered
unbuffered Table 50 tables Topology/ Trace
Length tables for additional information.
• +/- 0.025" max. within Pairs [Intra-pair]
• With-in +/- 1.0" of all strobes (DQS0-8) (strobe
length measured from IOP die to SDRAM)
• 1.0" to 2.0" longer than Add/CMD/Control
(Add/CMD/Control length measured from IOP die
to Register input)
• With-in +/- 1.0" of associated strobe (DQS) (strobe
length measured from IOP die to SDRAM)
• 1.0" to 2.0" longer than Add/CMD/Control from
(Add/CMD/Control length measured from IOP die
to SDRAM input)
• +/- 0.1" max. between the 3 pairs of Unbuffered
Clocks (clock length measured from IOP die to
SDRAM)
• For Registered: maximum of 3 pairs from IOP to
PLL
• For Unbuffered: maximum of 4 pairs.
All un-buffered clocks utilized in memory
implementations must be load balanced. Use
capacitors equal to the SDRAM's clock input
capacitance to balance loading across all the clocks
used. Topology shown is based on a Raw B
implementation. Refer to JEDEC Un-buffered DIMM
specs. for Raw Card C implementation specifics.
Memory Controller
Table 49 and
93