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7.7
DDR Termination Voltage
The V
TT
termination resistors. This tracking must be 50 percent of (V
temperature, and noise. It must maintain less than 40 mV offset from V
This voltage must be low-impedance and source-significant current. The source and sink DC
current for signal termination is at its absolute maximum current of 2.6 A-2.9 A for a 64/72-bit
DIMM.
7.8
DDR V
The
Figure 61
input leakage and small transients). It must track 50 percent of (V
temperature, and noise. Use a single source for V
multiple generators. Maintain 15-20 mils clearance around other nets. Use a distributed decoupling
scheme. Use a simple resistor divider with 1% or better accuracy.
Note: The 100 ohm resistors can be replaced with 1K +/- 1% resistors to minimize leakage current during
battery backup mode.
Figure 61.
DDR V
REF
DDR termination voltage must track the V
Voltage
REF
shows the DDR Vref voltage. The DDR V
Circuit
2.5/1.8V
0.1uF
Intel® 80331 I/O Processor Design Guide
and provide the termination voltage to the
DDQ
- V
) over voltage,
DDQ
SSQ
REF
is a low-current source (supplying
REF
-V
DDQ
SSQ
to eliminate variation and tracking of
REF
0.1uF
100 ohms
DDR VREF
0.1uF
100 ohms
Memory Controller
over these conditions.
) over voltage,
121
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