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Intel® 80331 I/O Processor Design Guide
Memory Controller
7.5.3
DIMM Layout Design
The following tables provide the source synchronous, clock and control layout guidelines when
laying out the board for DDRII 400 registered DIMMs. The guidelines were based on simulating
RawA and RawB DIMM topologies.
7.5.3.1
DDR II 400 DIMM Source Synchronous Routing
This section lists the recommendations for the DDR II 400 Source Synchronous Routing. These
signals include all the DQ/DQS/DM signals. Refer to
of the lengths and matching requirements.
®
Figure 49.
Intel
80331 I/O Processor DDRII 400 DIMM Source Synchronous Routing
104
DQS Group 1
DQS# Group 1
I/O Processor
DQ Group 2
DQS Group 2
DQS# Group 2
Figure 49
and
DQ Group 1
Y1 +/- 50 mils
8 lines
Y1
Y1+/-25 mils
X1 +/- 50 mils
8 lines
X1
X1+/-25 mils
2.0" - 8.0"
Table 58
for a block diagram
D
I
M
M
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