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Intel® 80331 I/O Processor Design Guide
Terminations
Table 3.
Terminations: Pull-up/Pull-down (Sheet 4 of 4)
Signal
P_M66EN
P_REQ#
M_CK[2:0], M_CK[2:0]#
DQS[8:0]#
DDRRES[2:1]
HPI#
P_BOOT16#
MEM_TYPE
RETRY
CORE_RST#
BRG_EN
DDRSLWCRES
DDRIMPCRES
ODT[1:0]
26
Pull-up or Pull-down
Resistor Value (in Ohms)
Refer to comments
Refer to comments
Refer to comments
Refer to Comments
• Refer to
Figure 8
for the
recommended
termination for DDRII
mode.
• When not in DDRII
mode these signals
have a 1.0 K pull-down.
8.2 K pull-up
1.5 K pull-down when
needed (refer to comments)
1.5 K pull-down when
needed (refer to comments)
1.5 K pull-down when
needed (refer to comments)
1.5 K pull-down when
needed (refer to comments)
1.5 K pull-down when
needed (refer to comments)
Refer to
Figure 9
Refer to
Figure 9
Connect to ODT on DIMM
terminated with 49.9 ohm
resistor to VTT
8.2 K pull-up is required when not already pulled up on the PCI bus.
An add-in card may rely on the motherboard to pull-up this signal.
8.2 K pull-up is required when not already pulled up on the PCI bus.
An add-in card may rely on the motherboard to pull-up this signal.
For M_CKs and M_CK#s not used leave these pins unconnected.
When not in DDRII mode these signals are NC's
Bus Width is latched on the rising (asserting) edge of P_RST#, it sets
the default bus width for the PBI Memory Boot window:
• 0 = 16 bits wide (Requires a pull-down resistor.)
• 1 = 8 bits wide (Default mode)
Muxed onto signal AD[4].
Memory Type: MEM_TYPE is latched on the rising (asserting) edge
of P_RST# and it defines the speed of the DDR SDRAM interface.
0 = DDR-II SDRAM at 400 MHz (Required pull-down resistor.)
1 = DDR SDRAM at 333 MHz (Default mode)
Muxed onto signal AD[2]
Configuration Retry Mode: RETRY is latched on the rising (asserting)
edge of P_RST# and determines when PCI interface of the ATU
disables PCI configuration cycles by signaling a retry until the
configuration cycle retry bit is cleared in the PCI configuration and
status register.
0 = Configuration Cycles enabled (Requires pull down resistor.)
1 = Configuration Retry enabled in the ATU and the Configuration.
(Default mode)
Muxed onto signal AD[6]
Core Reset Mode is latched on the rising (asserting) edge of P_RST#
and determines when the Intel
processor reset bit is cleared in PCI configuration and status register.
0 = Hold in reset. (Requires pull-down resistor.)
1 = Do not hold in reset. (Default mode)
Muxed onto signal AD[5]
Bridge Enable: BRG_EN latched at rising (deasserting) edge of
P_RST# and determines when the 80331 operates with PCI-to-PCI
Bridge.
0 = Disable Bridge, enable P_CLK input on S_CLKIN input.
(Requires pull-down resistor)
1 = Enabled Bridge. (Default mode)
Muxed onto signal AD[0]
When not used this pin is left as a "no connect".
Comments
®
™
XScale
core is held in reset until the
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