Embedded Ddr 333 Unbuffered Addr/Cmd Topology; Embedded Ddr 333 Unbuffered Address/Cmd Topology Lengths - Intel 80331 Design Manual

Intel® 80331 I/O Processor Design Guide
Memory Controller
Table 52.

Embedded DDR 333 Unbuffered Address/CMD Topology Lengths

Traces Description
TL1
TL2
TL3
TL4
TL5
TL6
TL7
TL8 Breakout
TL9 Lead-in
TL10 VTT
NOTE: All traces except breakout TL8 traces are of the same impedance and spacing requirements.
Figure 47.

Embedded DDR 333 Unbuffered ADDR/CMD Topology

98
Minimum Maximum
Layer
Length Length
Microstrip/
1.5" 1.67"
Strip
Microstrip 1.2 " 1.35"
Microstrip 0.5" 0.6"
0.3" 0.35"
0.14" 0.18"
0.32" 0.35"
0.25" 0.5"
Any 0" 0.5"
Microstrip/
1" 8"
Stripline
Microstrip 0.25" 0.5"
22 ohms
+/- 5%
TL9
TL8 TL7
Trace
Spacing
Impedance
45 ohms+/-15%
or 50 ohms 12 mils
+/-15%
Same as TL1 12 mils
Same as TL1 12 mils
Same as TL1 12 mils
Same as TL1 12 mils
Same as TL1 12 mils
Same as TL1 12 mils
5 mils
45 ohms+/-15%
or 50 ohms 12 mils
+/-15%
5 mils
VTT (1.25 V)
51 ohms
+/- 5%
TL1
TL10
TL2
Notes
TL1-TL6 as per JEDEC DDR1
Specifications (PC2700) to be
routed as T points
Fan out for series termination
(only for unbuffered)
Spacing: within the same
group 12 mils
With other groups 20 mils
Place in VTT Island
TL5
SDRAM Pin
TL3
SDRAM Pin
TL5
TL4
TL4
SDRAM Pin
TL5
TL3
SDRAM Pin
TL5
SDRAM Pin
TL5
TL3
SDRAM Pin
TL5
TL3
SDRAM Pin
TL6
TL3
SDRAM Pin
TL5
TL3
SDRAM Pin
TL5