Pci 33 Mhz Embedded Mode Topology; Pci 33 Mhz Embedded Mode Routing Topology; Pci 33 Mhz Embedded Routing Recommendations - Intel 80331 Design Manual

Intel® 80331 I/O Processor Design Guide
PCI-X Layout Guidelines
Table 24. PCI 33 MHz Slot Routing Recommendations (Sheet 2 of 2)
Trace Length TL2 to TL5
between connectors.
Trace Length TL_AD1 to
TL_AD5 from connector to
receiver
Length Matching
Requirements:
Number of vias
6.4.18

PCI 33 MHz Embedded Mode Topology

Figure 33
design.
Figure 33.

PCI 33 MHz Embedded Mode Routing Topology

Table 25. PCI 33 MHz Embedded Routing Recommendations (Sheet 1 of 2)
Parameter
Reference Plane
Breakout
Motherboard Trace
Impedance (microstrip and
stripline)
Add-in card Impedance
(microstrip and stripline)
Stripline Trace Spacing
Microstrip Trace Spacing
64
0.8" minimum - 1.5" maximum
0.75" minimum - 1.5" maximum
No length matching is required among datalines. For length matching for clocks,
refer clock guidelines
Four vias maximum
and Table 25 provides routing details for a topology with for an embedded PCI 33 MHz
Route over an unbroken ground plane
5 mils on 5 mils spacing. Maximum length of the breakout is 500 mils.
50 Ohms +/- 15%
60 Ohms +/- 15%
10 mils, from edge to edge
15 mils, from edge to edge
1.75" minimum - 2.75" maximum
Table 8.
Routing Guideline for Lower AD Bus