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7.3
DDR 333 Signal Integrity Simulation Conditions
•
Motherboard 50 ohm single ended impedance stackup +/- 15% tolerance.
•
Add-in Card 60 ohm single ended impedance stackup +/- 15% tolerance.
•
Clock Target Differential Impedance 100 ohms and 50 ohms single-ended impedance.
•
Memory Model Micron T17A_DQ and Intel generic models.
•
PLL Clock - Pericom* CDCBV857, PI6DCV16859.
•
DIMM models and topologies used the JEDEC model as a reference.
•
For unbuffered embedded and post PLL/register the standard recommendations were used as a
reference.
•
Spacing recommendations are for trace edge to edge except for differential pairs in which
center to center was specified.
•
Signal Quality analysis covered for Rising flight time, Falling flight time, Low to high
ring-back (noise margin high), High to Low ring-back (noise margin Low), and Low and High
Overshoot.
•
Crosstalk Analysis was performed for all the major interfaces with actual package models.
•
Frequency: 167MHz (DDR 333 MT/s).
•
Connector –E SPICE of DIMM Connector (Derived from SPICE Circuit)
•
Package - Actual extracted Package Model used.
The topologies simulated are listed in
Table 30.
Simulated DDR 333 Topologies
1. DQ/DQS
• Read- RAW A, RAWB
• Write -RAW A, RAW B
2. Clock
• Buffered
• Unbuffered
3. Address/CMD
• Registered
• Unbuffered - RAWA, RAWB
Table
30.
DIMM
Intel® 80331 I/O Processor Design Guide
Embedded
1. DQ/DQS
• Read- Single Bank
• Write - Single Bank
2. Clock
• Buffered
• Unbuffered
• Post-PLL
• PLL to SDRAM
• PLL to Register
• PLL to Feedback
3. Address/CMD
• Registered
• Unbuffered - Single bank ECC and non ECC
• Post Register - single bank ECC and non ECC
Memory Controller
69
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