Embedded Ddr 333 Buffered Clock Topology Lengths - Intel 80331 Design Manual

Intel® 80331 I/O Processor Design Guide
Memory Controller
Table 49.

Embedded DDR 333 Buffered Clock Topology Lengths

Traces Description
TL0 Breakout
TL1 Lead-in
TL2 Termination
TL0_PLL
FB
TL2_PLL
Termination
FB
TL3_PLL
FB
TL0_sdra
m
TL1_sdra
Termination
m
TL2_sdra
m
TL0_reg
TL1_reg
TL2_reg Termination
NOTES:
1. For any additional loading configurations use same recommendations of TL1_SDRAM and TL2_SDRAM
values.
2. JEDEC DDR1 (PC2700) registered DIMM recommendations are referenced for post PLL configurations.
94
Min
Layer
Length Length
Microstrip/
0.5"
Stripline
Microstrip/
2" 8"
Stripline
0.2"
2" 3"
0.3"
0.05" 0.09"
2.5"
0.5" 0.58"
0.29" 0.3"
0.05"
2.71" 2.72"
0.20" 0.22"
Max Trace
Spacing
Impedance
5 mils
Differential
20 mils
Impedance of
from
100 ohms +/-
others
15%
5 mils
20 mils
Same as TL1 from
others
Same as TL1
Same as TL1
Same as TL1
Same as TL1
Notes
Differential Routing
Route per DDR1 JEDEC
Route per DDR1 JEDEC
Route per DDR1 JEDEC
Route per DDR1 JEDEC
Route per DDR1 JEDEC
Route per DDR1 JEDEC
Route per DDR1 JEDEC
Route per DDR1 JEDEC
Route per DDR1 JEDEC