Table of Contents
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Intel® 80331 I/O Processor Design Guide
Contents
Tables
1
Terminology and Definitions ....................................................................................................... 12
2
FC-style, H-PBGA Package Dimensions.................................................................................... 17
3
Terminations: Pull-up/Pull-down ................................................................................................. 23
4
Decoupling Recommendations................................................................................................... 34
5
Motherboard Stack Up, Stripline and Microstrip ......................................................................... 37
6
Adapter Card Stack Up, Microstrip and Stripline ........................................................................ 39
7
PCI-X Slot Guidelines................................................................................................................. 43
8
PCI-X Clock Layout Requirements Summary ............................................................................ 46
9
PCI-X 133 MHz Single Slot Routing Recommendations ............................................................ 48
10 Embedded PCI-X 133 MHz Routing Recommendations ............................................................ 49
11 Embedded PCI-X 133 MHz Alternate Topology Routing Recommendations............................. 50
12 Embedded and Slot PCI-X 133 MHz Routing Recommendations.............................................. 51
13 Embedded and Slot PCI-X 133 MHz Routing Recommendations.............................................. 52
14 PCI-X 100 MHz Slot Topology Routing Recommendations ....................................................... 53
15 PCI-X 100 MHz Embedded Routing Recommendations ............................................................ 54
16 Combination of Slot and Embedded PCI-X 100 MHz Routing Recommendations .................... 55
17 Combination of Slot and Embedded PCI-X 100 MHz Routing 2 Recommendations ................. 56
18 PCI-X 66 MHz Slot Routing Recommendations ......................................................................... 57
19 PCI-X 66 MHz Embedded Routing Recommendations .............................................................. 58
20 PCI-X 66 MHz Mixed Mode Routing Recommendations............................................................ 59
21 PCI 66 MHz Slot Table ............................................................................................................... 60
22 PCI 66 MHz Embedded Table.................................................................................................... 61
23 PCI 66 MHz Mixed Mode Table.................................................................................................. 62
24 PCI 33 MHz Slot Routing Recommendations............................................................................. 63
25 PCI 33 MHz Embedded Routing Recommendations ................................................................. 64
26 PCI 33 MHz Mixed Mode Routing Recommendations ............................................................... 65
27 DDR Bias Voltages ..................................................................................................................... 67
28 DDR II Bias Voltage.................................................................................................................... 67
29 Core Speed and Memory Configuration ..................................................................................... 68
30 Simulated DDR 333 Topologies ................................................................................................. 69
31 Example Topologies for DDR Trace ........................................................................................... 71
32 x64 DDR Memory Configuration................................................................................................. 72
33 x72 DDR Memory Configuration................................................................................................. 72
34 Source Synchronous Termination Requirements ....................................................................... 73
35 Source Synchronous Routing Recommendations ...................................................................... 74
36 DIMM DQ/DQS Topology Lengths ............................................................................................. 75
37 Die to Ball Internal Lengths ........................................................................................................ 75
38 DIMM DQ/DQS Split Termination Topology Lengths ................................................................. 80
39 DIMM Clocked Signal Group Termination .................................................................................. 81
40 Clock Signal Group Registered/Unbuffered DIMM Routing Requirements ................................ 82
41 Registered DIMM Clock Topology Lengths ................................................................................ 83
42 DDR 333 Unbuffered DIMM Clock Topology Lengths ................................................................ 84
43 Source Clocked Signal Routing .................................................................................................. 85
44 Control Signals Routing Guidelines ............................................................................................ 86
45 Control Signal DIMM Topology Lengths ..................................................................................... 88
46 DDR 333 Embedded Source Synchronous Routing Recommendations.................................... 89
47 Embedded DDR 333 DQ/DQS Topology Lengths...................................................................... 91
48 DDR 333 Embedded Registered/Unbuffered Clock Routing Recommendations ....................... 93
8
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